After partitioning the circuit into smaller modules and floorplanning the layout to determine block outlines and pin locations,
seeks to determine the locations of standard cells or logic elements within each block while addressing optimization objectives, e.g., minimizing the total length of connections between elements. Specifically,
(Sec. 4.3) assigns general locations to movable objects, while
(Sec. 4.4) refines object locations to legal cell sites and enforces nonoverlapping constraints. The detailed locations enable more accurate estimates of circuit delay for the purpose of timing optimization.