Han–Carlson adder based high-speed Vedic multiplier for complex multiplication

Critical role is played by multipliers in modern digital signal processing systems. The overall system is affected by multipliers in terms of speed and computational complexity. In this paper, a Han–Carlson adder (HCA) based high-speed Vedic multiplier is proposed. The proposed Vedic multiplier uses Urdhva–Tiryakbhyam sutra of Vedic multiplication. Han–Carlson adder is one of the parallel-prefix adders which provides high-speed to the proposed multiplier architecture. Proposed architecture of 64 × 64 bit Vedic multiplier is implemented using Xilinx ISE 14.2 navigator in VHDL. The implementation results of proposed architecture are compared with conventional Vedic multipliers with different adders which show that the conventional multipliers is having larger time delay as compared to proposed multiplier. Furthermore, complex multiplication architectures, using three and four 32 × 32 bit proposed Vedic multipliers are also implemented. The results of these complex multiplication architectures are also compared with conventional Booth multiplier and Array multiplier based architectures which show that the complex multiplication using proposed architecture provides improved delay, low hardware (LUTs) and low complexity.