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2024 | OriginalPaper | Buchkapitel

Hardware Security for IC Piracy: Logic Locking Past, Present and Opportunity

verfasst von : Aditya Kalyani

Erschienen in: Advances in Microelectronics, Embedded Systems and IoT

Verlag: Springer Nature Singapore

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Abstract

Logic locking is an emerging technique for securing the IP from hardware security threats at the IC manufacturing supply chain. Over a decade, the research studies have investigated the metrics to assess the efficacy, the impact of locking at different levels of abstraction, threat model definition, resiliency against physical attacks and tampering. In this survey paper, we classify the existing defences and attacks to capture benefits from the logic locking techniques for IP protection. This survey paper serves as a guide to quickly navigate and identify the state-of-the-art studies on logic locking techniques.

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Literatur
1.
Zurück zum Zitat Weste N, Harris D (2015) CMOS VLSI design: a circuits and systems perspective. Pearson Education India Weste N, Harris D (2015) CMOS VLSI design: a circuits and systems perspective. Pearson Education India
2.
Zurück zum Zitat Rajendran, Sam M, Sinanoglu O, Karri R (2013) Security analysis of integrated circuit camouflaging. In: Proceedings of the ACM SIGSAC conference on computer and communications security, pp 709–720 Rajendran, Sam M, Sinanoglu O, Karri R (2013) Security analysis of integrated circuit camouflaging. In: Proceedings of the ACM SIGSAC conference on computer and communications security, pp 709–720
3.
Zurück zum Zitat Rajendran J, Sinanoglu O, Karri R (2013) VLSI testing based security metric for IC camouflaging. In: IEEE international test conference (ITC), pp 1–4 Rajendran J, Sinanoglu O, Karri R (2013) VLSI testing based security metric for IC camouflaging. In: IEEE international test conference (ITC), pp 1–4
4.
Zurück zum Zitat Yasin M, Mazumdar B, Sinanoglu O, Rajendran J (2016) CamoPerturb: secure IC camouflaging for minterm protection. In: IEEE/ACM international conference on computer-aided design (ICCAD), pp 1–8 Yasin M, Mazumdar B, Sinanoglu O, Rajendran J (2016) CamoPerturb: secure IC camouflaging for minterm protection. In: IEEE/ACM international conference on computer-aided design (ICCAD), pp 1–8
5.
Zurück zum Zitat Li M, Shamsi K, Meade T, Zhao Z, Yu B, Jin Y, Pan DZ (2017) Provably secure camouflaging strategy for IC protection. IEEE Trans CAD Integr Circ Syst 38(8):1399–1412CrossRef Li M, Shamsi K, Meade T, Zhao Z, Yu B, Jin Y, Pan DZ (2017) Provably secure camouflaging strategy for IC protection. IEEE Trans CAD Integr Circ Syst 38(8):1399–1412CrossRef
6.
Zurück zum Zitat Rajendran J, Sinanoglu O, Karri R (2013) Is split manufacturing secure? In: Design, automation and test in Europe conference and exhibition (DATE), pp 1259–1264 Rajendran J, Sinanoglu O, Karri R (2013) Is split manufacturing secure? In: Design, automation and test in Europe conference and exhibition (DATE), pp 1259–1264
7.
Zurück zum Zitat Imeson F, Emtenan A, Garg S, Tripunitara M (2013) Securing computer hardware using 3D integrated circuit (IC) technology and split manufacturing for obfuscation. In: USENIX security symposium, pp 495–510 Imeson F, Emtenan A, Garg S, Tripunitara M (2013) Securing computer hardware using 3D integrated circuit (IC) technology and split manufacturing for obfuscation. In: USENIX security symposium, pp 495–510
8.
Zurück zum Zitat Vaidyanathan K, Das B, Sumbul E, Liu R, Pileggi L (2014) Building trusted ICs using split fabrication. In: IEEE international symposium on hardware-oriented security and trust (HOST), pp 1–6 Vaidyanathan K, Das B, Sumbul E, Liu R, Pileggi L (2014) Building trusted ICs using split fabrication. In: IEEE international symposium on hardware-oriented security and trust (HOST), pp 1–6
9.
Zurück zum Zitat Lee J, Tehranipoor M, Patel C, Plusquellic J (2007) Securing designs against scan-based side-channel attacks. IEEE Trans Dependable Secure Comput 4(4):325–336CrossRef Lee J, Tehranipoor M, Patel C, Plusquellic J (2007) Securing designs against scan-based side-channel attacks. IEEE Trans Dependable Secure Comput 4(4):325–336CrossRef
10.
Zurück zum Zitat Roy J, Koushanfar F, Markov IL (2008) EPIC: ending piracy of integrated circuits. In: Design, automation and test in Europe conference (DATE), pp 1069–1074 Roy J, Koushanfar F, Markov IL (2008) EPIC: ending piracy of integrated circuits. In: Design, automation and test in Europe conference (DATE), pp 1069–1074
11.
Zurück zum Zitat Rajendran J, Pino Y, Sinanoglu O, Karri R (2012) Security analysis of logic obfuscation. In: Design automation conference (DAC), pp 83–89 Rajendran J, Pino Y, Sinanoglu O, Karri R (2012) Security analysis of logic obfuscation. In: Design automation conference (DAC), pp 83–89
12.
Zurück zum Zitat Guin U, Shi Q, Forte D, Tehranipoor M FORTIS: a comprehensive solution for establishing forward trust for protecting IPs and ICs. ACM Trans Des Autom Electron Syst (TODAES) Guin U, Shi Q, Forte D, Tehranipoor M FORTIS: a comprehensive solution for establishing forward trust for protecting IPs and ICs. ACM Trans Des Autom Electron Syst (TODAES)
13.
Zurück zum Zitat Limaye N, Sengupta A, Nabeel M, Sinanoglu O (2019) Is robust design-for-security robust enough? Attack on locked circuits with restricted scan chain access. In: IEEE/ACM international conference on computer-aided design (ICCAD), pp 1–8 Limaye N, Sengupta A, Nabeel M, Sinanoglu O (2019) Is robust design-for-security robust enough? Attack on locked circuits with restricted scan chain access. In: IEEE/ACM international conference on computer-aided design (ICCAD), pp 1–8
14.
Zurück zum Zitat Kamali HM, Azar KZ, Homayoun H, Sasan A (2020) On designing secure and robust scan chain for protecting obfuscated logic. In: Great Lakes symposium on VLSI (GLSVLSI), pp 217–222 Kamali HM, Azar KZ, Homayoun H, Sasan A (2020) On designing secure and robust scan chain for protecting obfuscated logic. In: Great Lakes symposium on VLSI (GLSVLSI), pp 217–222
15.
Zurück zum Zitat Massad, Garg S, Tripunitara M (2015) Integrated circuit (IC) decamouflaging: reverse engineering camouflaged ICs within minutes. In: Network and distributed system security symposium Massad, Garg S, Tripunitara M (2015) Integrated circuit (IC) decamouflaging: reverse engineering camouflaged ICs within minutes. In: Network and distributed system security symposium
16.
Zurück zum Zitat Yasin M, Mazumdar B, Sinanoglu O, Rajendran J Camo Perturb: secure IC camouflaging for minterm protection. In: IEEE/ACM Inter Yasin M, Mazumdar B, Sinanoglu O, Rajendran J Camo Perturb: secure IC camouflaging for minterm protection. In: IEEE/ACM Inter
17.
Zurück zum Zitat Rajendran J, Zhang H, Zhang C, Rose GS, Pino Y, Sinanoglu O, Karri R (2015) Fault analysis-based logic encryption. IEEE Trans Comput 64(2):410–424MathSciNetCrossRef Rajendran J, Zhang H, Zhang C, Rose GS, Pino Y, Sinanoglu O, Karri R (2015) Fault analysis-based logic encryption. IEEE Trans Comput 64(2):410–424MathSciNetCrossRef
18.
Zurück zum Zitat Riedel MD, Bruck J (2003) The synthesis of cyclic combinational circuits. In: Design automation conference (DAC), pp 163–168 Riedel MD, Bruck J (2003) The synthesis of cyclic combinational circuits. In: Design automation conference (DAC), pp 163–168
19.
Zurück zum Zitat Roshanisefat S, Kamali HM, Sasan A (2018) SRCLock: SAT-resistant cyclic logic locking for protecting the hardware. In: Proceedings of the on Great Lakes symposium on VLSI (GLSVLSI), pp 153–158 Roshanisefat S, Kamali HM, Sasan A (2018) SRCLock: SAT-resistant cyclic logic locking for protecting the hardware. In: Proceedings of the on Great Lakes symposium on VLSI (GLSVLSI), pp 153–158
20.
Zurück zum Zitat Roshanisefat S, Kamali HM, Homayoun H, Sasan A (2020) SAT-hard cyclic logic obfuscation for protecting the IP in the manufacturing supply chain. IEEE Trans Very Large Scale Integr (VLSI) Syst 28(4):954–967 Roshanisefat S, Kamali HM, Homayoun H, Sasan A (2020) SAT-hard cyclic logic obfuscation for protecting the IP in the manufacturing supply chain. IEEE Trans Very Large Scale Integr (VLSI) Syst 28(4):954–967
21.
Zurück zum Zitat Zhang D, He M, Wang X, Tehranipoor M (2017) Dynamically obfuscated scan for protecting IPs against scan-based attacks throughout supply chain. In: VLSI test symposium (VTS), pp 1–6 Zhang D, He M, Wang X, Tehranipoor M (2017) Dynamically obfuscated scan for protecting IPs against scan-based attacks throughout supply chain. In: VLSI test symposium (VTS), pp 1–6
22.
Zurück zum Zitat Chakraborty RS, Bhunia S (2009) HARPOON: an obfuscation based SoC design methodology for hardware protection. IEEE Trans Comput Aided Des Integr Circ Syst 28(10):1493–1502CrossRef Chakraborty RS, Bhunia S (2009) HARPOON: an obfuscation based SoC design methodology for hardware protection. IEEE Trans Comput Aided Des Integr Circ Syst 28(10):1493–1502CrossRef
23.
Zurück zum Zitat Desai AR, Hsiao MS, Wang C, Nazhandali L, Hall S (2013) Interlocking obfuscation for anti-tamper hardware. In: Proceedings of the cyber security and information research workshop, pp 1–8 Desai AR, Hsiao MS, Wang C, Nazhandali L, Hall S (2013) Interlocking obfuscation for anti-tamper hardware. In: Proceedings of the cyber security and information research workshop, pp 1–8
24.
Zurück zum Zitat Koushanfar (2017) Active hardware metering by finite state machine obfuscation. In: Hardware protection through obfuscation, pp 161–187 Koushanfar (2017) Active hardware metering by finite state machine obfuscation. In: Hardware protection through obfuscation, pp 161–187
26.
Zurück zum Zitat Jarvis R, McIntyre M (2007) Split manufacturing method for advanced semiconductor circuits. US Patent 7,195,931 Jarvis R, McIntyre M (2007) Split manufacturing method for advanced semiconductor circuits. US Patent 7,195,931
27.
Zurück zum Zitat Yasin M, Mazumdar B, Sinanoglu O, Rajendran J (2017) Security analysis of anti-SAT. In: Asia and South Pacific design automation conference (ASP-DAC), pp 342–347 Yasin M, Mazumdar B, Sinanoglu O, Rajendran J (2017) Security analysis of anti-SAT. In: Asia and South Pacific design automation conference (ASP-DAC), pp 342–347
Metadaten
Titel
Hardware Security for IC Piracy: Logic Locking Past, Present and Opportunity
verfasst von
Aditya Kalyani
Copyright-Jahr
2024
Verlag
Springer Nature Singapore
DOI
https://doi.org/10.1007/978-981-97-0767-6_1