2011 | OriginalPaper | Buchkapitel
Heterogeneous FPGA Exploration Environment
verfasst von : Husain Parvez, Habib Mehrez
Erschienen in: Application-Specific Mesh-based Heterogeneous FPGA Architectures
Verlag: Springer New York
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This chapter presents an environment for the exploration of 2D mesh-based heterogeneous FPGA architectures. An architecture description mechanism allows to define various architectural parameters including definition of new heterogeneous blocks, position of these blocks on the architecture and the choice of routing network. Once the initial architecture is defined, a software flow places and routes a target netlist on the generated architecture. The placement algorithm not only changes the position of netlist instances on their respective blocks on the architecture, but it also refines the position of blocks on the architecture. The position of blocks on the FPGA architecture, also called as floor-planning, can also be optimized for multiple netlists. A set of DSP test-benches are used to compare the effect of different floor-plannings on the area of mesh-based heterogeneous FPGA architectures.