Heterogeneous Reconfigurable Processors for Real-Time Baseband Processing

This book discusses an interdisciplinary study in wireless communication and Very-large-scale integration (VLSI) design, more specifically, implementation of digital baseband processing using reconfigurable architectures. Development of such kind of systems, sometimes referred to as baseband processors [15] or Software-defined radio (SDR) platforms [8], is an important and challenging subject, especially for small-scale base stations (e.g., femtocells) and mobile terminals that must provide reliable services under various operating scenarios with low power consumption.

Since the invention of the integrated circuit in the 1950s, there has been explosive developments of electronic circuits. Over the last decades, the amount of transistors, which are the fundamental elements of digital and analog circuits, fitting on a single silicon die has increased exponentially, from a few thousands to billions to date. This trend was already observed in 1965 [15] by Intel’s co-founder Gordon E. Moore and later came to be known as “Moore’s law” coined by Carver Mead. Moore’s law has held true since then and is a driving force of the advancements of Very-large-scale integration (VLSI) design [11].

Wireless communication has been experiencing explosive growth since its invention. The wireless landscape has been broadened by incorporating more than basic voice services and low data rate transmissions. Taking cellular systems as an example, the fourth generation (4G) mobile communication technology promises to provide broadband Internet access in mobile terminals with up to gigabit-per-second downlink data rate [6]. Compared to the 9.6 kbit/s data services in its 2G predecessor Global system for mobile communications (GSM), 4G systems enhance the data rate by 5 orders of magnitude. This data rate boost is a result of innovations in wireless technology, such as Orthogonal frequency division multiplexing (OFDM) and Multiple-input multiple-output (MIMO). The high speed data links together with advancements in mobile terminals (e.g., phones, tablet computers, and wearable devices) have opened up a whole new world for wireless communication and changed everyone’s life. Besides conventional usage like Internet streaming and multimedia playback, interdisciplinary applications like mobile health (mHealth) [19] are emerging. New applications set new demands on wireless services, pushing forward technology developments.

Emerging as a prominent technology, reconfigurable architectures have the potential of combining high hardware flexibility with high performance data processing. Conventional fine-grained architectures, such as Field-programmable gate arrays (FPGAs), provide great flexibility by allowing bit-level manipulations in system designs. However, the fine-grained configurability results in long configuration time and poor area and power efficiency, and thus restricts the usage of such architectures in time-critical and area/power-limited applications. To address these issues, recent work focuses on coarse-grained architectures, aiming to provide a balance between flexibility and hardware efficiency by adopting word-level data processing. In this chapter, a coarse-grained dynamically reconfigurable cell array architecture is introduced. The architecture is constructed from an array of heterogeneous functional units communicating via hierarchical network interconnects. The strength of the architecture lies in simplified data sharing achieved by decoupled processing and memory cells, substantial communication cost reduction obtained by a hierarchical network structure, and fast context switching enabled by a unique run-time reconfiguration mechanism. The presented reconfigurable cell array serves as a baseline architecture for two case studies presented in Chaps. 5 and 6.

To demonstrate flexibility and performance of the reconfigurable cell array architecture introduced in Chap. 4, this chapter presents a case study of the platform configured for concurrent processing of multiple radio standards. Flexibility of the architecture is demonstrated by performing time synchronization and Carrier frequency offset (CFO) estimation for multiple Orthogonal frequency division multiplexing (OFDM)-based standards. As a proof-of-concept, this study focuses on three contemporarily widely used radio standards, 3GPP Long term evolution (LTE), IEEE 802.11n, and Digital video broadcasting for handheld (DVB-H). The employed reconfigurable cell array, containing 2 × 2 resource cells, supports all three standards and is capable of processing two concurrent data streams. The cell array is implemented in a 65 nm CMOS technology, resulting in an area of 0.48 mm² and a maximum clock frequency of 534 MHz. Dynamic configuration of the cell array enables run-time switching between different standards and allows adoption of different algorithms on the same platform. Taking advantage of the in-cell configuration scheme (described in Chap. 4), context switching between different operation scenarios requires at most 11 clock cycles. The implemented 2 × 2 cell array is fabricated as a part of a Digital front-end (DFE) Receiver and is measured as a standalone module via an on-chip serial debugging interface. Running at 10 MHz clock frequency and at 1.2 V supply voltage, the array reports a maximum power consumption of 2.19 mW during the processing of IEEE 802.11n data receptions and 2 mW during hardware configurations.

Driven by the requirement of multi-dimensional computing in contemporary wireless communication technologies, reconfigurable platforms have come to the era of vector-based architectures. In this chapter, the reconfigurable cell array developed in Chaps. 4 and 5 is extended with extensive vector computing capabilities, aiming for high-throughput baseband processing in MIMO-OFDM systems. Besides the heterogeneous and hierarchical resource deployments, a vector-enhanced SIMD structure and various memory access schemes are employed. These architectural enhancements are designed to suffice stringent computational requirements while retaining high flexibility and hardware efficiency. Implemented in a 65 nm CMOS technology, the cell array occupies 8.88 mm² core area. To illustrate its performance and flexibility, three computationally intensive blocks, namely channel estimation, channel matrix pre-processing, and symbol detection, of a 4 × 4 MIMO processing chain in a 20 MHz 64-QAM Long term evolution-advanced (LTE-A) downlink are mapped and processed in real-time. Operating at 500 MHz and 1.2 V voltage supply, the achieved throughput is 367.88 Mb/s and the average power consumption is 548.78 mW. The corresponding energy consumption for processing one information bit is 1.49 nJ. Comparing to state-of-the-art implementations, the presented solution outperforms related programmable platforms by several orders of magnitude in energy efficiency, and achieves similar level of area and energy efficiency to that of ASICs.

Wireless communication technology is evolving at a fast pace to meet requirements of emerging applications, such as ultra-high resolution video, cloud computing, internet of things, etc. For example, it took only 2 years for cellular systems to evolve from LTE to LTE-A, delivering a 10 × increase in data rates. Almost at the same time that the first LTE-A service was launched, people are talking about next-generation (5G) wireless communication systems [3]. The coming 5G communication aims to connect tens of billions of devices with some reaching several gigabit-per-second data rates and milliseconds service latency. On the other hand, bandwidth is a scare resource, demanding revolution in wireless communication technologies to achieve these aggressive targets. Technologies being discussed include small-cell networks [7], millimeter wave communication [14], interference cancellation (e.g., full-duplex transmission [2]), advanced waveforms [6] (e.g., Generalized Frequency Division Multiplexing, Universal Filtered Multi-carrier, Filter-Bank based Multi-Carrier, Bi-orthogonal Frequency Division Multiplexing), Massive MIMO [4, 16], etc. Among those, Massive MIMO has been widely accepted, both in academia and industry, as one of the promising candidates for 5G. 3GPP is developing 3D channel models for this new MIMO technique. Studies for the Time-division duplexing (TDD) Massive MIMO have been initiated for 3GPP Release 13. In this chapter, we will focus on the Massive MIMO technology, discussing its basic concepts, state-of-the-art research progress, key signal processing in the digital baseband, as well as new challenges for designing reconfigurable architectures for its baseband implementation.

Coarse-grained reconfigurable architectures (CGRAs) emerge as a new class of hardware platforms, designed to bridge the gap of computational performance, hardware efficiency, and flexibility among conventional architectures such as Application-specific integrated circuits (ASICs), Field-programmable gate arrays (FPGAs), and Digital signal processors (DSPs). The strength of CGRAs lies in the capability of allocating hardware resources dynamically to accomplish current computational demands. In addition, hardware efficiency with respect to area and power consumption is substantially improved in comparison to FPGAs, thanks to the word-level data manipulations.