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Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob­ lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Introduction

Abstract
Testing for hardware faults is of major importance in ensuring reliable operation of digital circuits [Bre76,Fuj86]. A circuit must normally be tested during several phases of its production, and also while it is being used in the field, to verify that it is working according to specifications. In the last two decades, circuit design and device fabrication processes have advanced rapidly, resulting in very large-scale integrated (VLSI) circuits containing thousands or millions of transistors. The large number of components in VLSI circuits has greatly increased the importance and difficulty of testing such circuits.
Debashis Bhattacharya, John P. Hayes

Chapter 2. Circuit and Fault Modeling

Abstract
This chapter begins with a brief introduction of the vector sequence (VS) notation which will be used in this book as a tool for describing the behavior of high-level components, as well as for representing the faults and test patterns generated at different levels of abstraction. The general high-level circuit and fault modeling techniques are then presented. The chapter concludes with a detailed study of model construction at different abstraction levels for the special case of k-regular circuits. This illustrates the advantages of our approach over conventional modeling techniques.
Debashis Bhattacharya, John P. Hayes

Chapter 3. Hierarchical Test Generation

Abstract
A test generation procedure is now presented which utilizes the hierarchical circuit and fault models developed in the previous chapter. It aims to exploit the possibility of detecting a significant percentage of the SSL faults by generating tests for total bus faults in the high-level model of a circuit. By effectively merging sets of SSL faults that can be tested in parallel, the number of target faults is reduced, as is the overall test generation effort. Tests for faults that cannot be directly handled can then be obtained by applying the same test generation procedure to a gate-level model of the circuit. Thus, the test generation technique presented here is truly hierarchical, i.e., invariant with respect to the level of the circuit and fault model used, a feature that sets it apart from most other test generation procedures. Moreover, at the gate level total bus faults are the same as SSL faults, implying that the hierarchical test generation technique allows us to obtain complete SSL fault coverage while generating tests for total bus faults only. Experimental results for sample circuits are presented, which show that this approach results in complete test sets for SSL faults that are almost always smaller than those generated by conventional methods.
Debashis Bhattacharya, John P. Hayes

Chapter 4. Design for Testability

Abstract
This chapter investigates some design methods aimed at making logic circuits more amenable to testing using the test generation technique proposed in Chapter 3. It is clear from the previous two chapters that this approach is particularly well suited to circuits such as ripple-carry adders and parity checkers which contain repeated subcircuits interconnected in a regular fashion. A bus-oriented high-level model can be easily constructed following the procedure PSC of Fig. 2.17, so that a test set for an total bus faults in the resulting model detects all, or nearly all, SSL faults in the circuit. The scope of our testing methodology can be broadened considerably by formulating some design-for-testability techniques for circuits like carry-lookahead generators, counters, and decoders, etc., which take the form of slightly irregular array or tree circuits. The presence of irregularity makes the construction of high-level models for the unmodified circuits difficult, and complicates test generation. In this chapter, we consider redesigning circuits of this sort to enhance their regularity, and make them better suited to test generation using hierarchical approaches.
Debashis Bhattacharya, John P. Hayes

Chapter 5. Concluding Remarks

Summary
We have attempted to demonstrate the usefulness of bus-oriented high-level circuit and fault models in reducing the test set size, as well as the test generation time, for large digital circuits. Our circuit and fault models represent natural generalizations of the classical gate-level models. We have presented a high-level algorithm VPODEM which generates tests for total bus faults in the high-level circuit models. This algorithm assigns vectors to buses in the high-level model, the vectors being represented and manipulated using the vector sequence notation. The circuit and fault models, as well as the test generation algorithm, reduce to classical ones if components are restricted to single gates, and bus sizes are restricted to one. This provides a truly hierarchical approach to test generation for large circuits, in that SSL faults not detected by tests generated using the high-level models can be detected using the same algorithm and gate-level models of the circuit under test. Experimental results presented for some representative general circuits show that, in almost all the cases considered, the hierarchical approach leads to test sets that are less than half the size of test sets obtained using traditional techniques alone.
Debashis Bhattacharya, John P. Hayes

Backmatter

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