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Erschienen in:
2015 | OriginalPaper | Buchkapitel
15. High Level Design
verfasst von : Philip Andrew Simpson
Erschienen in: FPGA Design
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Abstract
High level design, which is often referred to as behavioral synthesis has a growing adoption in FPGA based system designs. As the technology has matured, the quality of the results has improved to the point that in many cases it can equal the results achieved with hand optimized RTL design, but in a fraction of the development time. One of the reasons for the improvement is that there has been a realization among the solution providers and the end users of these tools that one solution will not satisfy all class of designs. The tools have become focused on certain application areas and provide great benefit when used in these areas.