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Über dieses Buch

This book describes the optimized implementations of several arithmetic datapath, controlpath and pseudorandom sequence generator circuits for realization of high performance arithmetic circuits targeted towards a specific family of the high-end Field Programmable Gate Arrays (FPGAs). It explores regular, modular, cascadable and bit-sliced architectures of these circuits, by directly instantiating the target FPGA-specific primitives in the HDL. Every proposed architecture is justified with detailed mathematical analyses. Simultaneously, constrained placement of the circuit building blocks is performed, by placing the logically related hardware primitives in close proximity to one another by supplying relevant placement constraints in the Xilinx proprietary “User Constraints File”. The book covers the implementation of a GUI-based CAD tool named FlexiCore integrated with the Xilinx Integrated Software Environment (ISE) for design automation of platform-specific high-performance arithmetic circuits from user-level specifications. This tool has been used to implement the proposed circuits, as well as hardware implementations of integer arithmetic algorithms where several of the proposed circuits are used as building blocks. Implementation results demonstrate higher performance and superior operand-width scalability for the proposed circuits, with respect to implementations derived through other existing approaches. This book will prove useful to researchers, students and professionals engaged in the domain of FPGA circuit optimization and implementation.



Chapter 1. Introduction

This chapter presents a concise overview of FPGA-based architecture design. Certain existing research work behind proposing new FPGA architectures and CAD heuristics to overcome the design limitations have been discussed. It also unfolds the limitations of the FPGA CAD tool that are currently popular for arithmetic core generation. A methodology that uses the target FPGA specific primitive instantiation-based approach and constrained placement exercise has been proposed as a superior alternative in comparison to design implementations available in literature. The major contributions of this book have also been listed.

Ayan Palchaudhuri, Rajat Subhra Chakraborty

Chapter 2. Architecture of Target FPGA Platform

This chapter provides an insight into the architecture of Configurable Logic Blocks (CLBs), the basic building blocks of a FPGA, including details of the Look-Up Tables, wide function multiplexers,

Wide function multiplexers


chains, flip-flops, and DSP



. It also gives an overview of the different modes of implementation supported by Xilinx ISE to realize arithmetic functions.

Ayan Palchaudhuri, Rajat Subhra Chakraborty

Chapter 3. A Fabric Component Based Design Approach for High-Performance Integer Arithmetic Circuits

This chapter elaborates on some useful guidelines that can be helpful for compact and high-performance realization of circuits on modern high-end FPGAs from Xilinx. It involves manipulation of the Boolean equations

a priori

in the HDL circuit descriptions to forms that can be optimally mapped to the native target architecture by the CAD software. Although the guidelines are relatively simple, they are extremely useful in the efficient realization of numerous arithmetic circuits which can be constructed using the “bit-sliced” design paradigm.

Ayan Palchaudhuri, Rajat Subhra Chakraborty

Chapter 4. Architecture of Datapath Circuits

This chapter discusses some common arithmetic datapath circuits which can significantly contribute to the critical path delay, either due to their long, cascading path delay, or undesirable inference of logic elements and their irregular placement on the Xilinx fabric logic. We present pipelined implementations of arithmetic datapath circuits, which when combined with their constrained and careful placement on the fabric logic, significantly improve their performance. Simultaneously, we present the associated mathematical analyses and proofs of correctness for the proposed architecture.

Ayan Palchaudhuri, Rajat Subhra Chakraborty

Chapter 5. Architecture of Controlpath Circuits

This chapter explores the mathematical analyses and bit-sliced architectures of the pipelined implementations of two controlpath circuits:

integer comparator


loadable bidirectional counter

supported by the


CAD tool currently.

Ayan Palchaudhuri, Rajat Subhra Chakraborty

Chapter 6. Compact FPGA Implementation of Linear Cellular Automata

Cellular Automata (CA) have been proposed as popular VLSI primitives owing to their regular, cascadable structure, and supposedly local interconnects. However, rather surprisingly, the published literature does not stress that the regularity and locality of interconnects is often more


rather than being of


nature, and requires proper design methodologies to harness the advantage of CA in practical circuits. We address this issue with a case study of a one-dimensional (1-D) CA, and develops a methodology for the physical realization of such circuits. The main idea is to make optimal use of the underlying architecture, especially the hardware logic resources available in






, coupled with direct primitive


Primitive instantiation

and constrained


Constrained placement

of the logic elements.

Ayan Palchaudhuri, Rajat Subhra Chakraborty

Chapter 7. Design Automation and Case Studies

All the architectures proposed in the previous chapters have been realized using the bit-sliced design paradigm. The architectures are very regular in their structures, thereby serving as a motivation to automate the generation of the arithmetic circuit descriptions for the target FPGA platform. In this chapter, we will introduce the proposed

CAD tool

CAD tool

for design automation named


. We also present two relevant case studies comprising of multiple modules, whose HDL and placement constraints can be generated using



Ayan Palchaudhuri, Rajat Subhra Chakraborty

Chapter 8. Conclusions and Future Work

This chapter summarizes the contributions of this book. It also provides certain important pointers to potential future research direction in the field of FPGA-based arithmetic circuit design.

Ayan Palchaudhuri, Rajat Subhra Chakraborty


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