Skip to main content
Fachgebiete
Automobil + Motoren Bauwesen + Immobilien Business IT + Informatik Elektrotechnik + Elektronik Energie + Nachhaltigkeit Finance + Banking Management + Führung Marketing + Vertrieb Maschinenbau + Werkstoffe Versicherung + Risiko
DE
EN
Bücher
Zeitschriften
Themenseiten
Organisationspsychologie Projektmanagement Marketing Smart Manufacturing
Weitere Formate
Podcasts Webinare Technik Webinare Wirtschaft Kongresse Veranstaltungskalender Awards
Jetzt Einzelzugang starten
Zugang für Unternehmen
Referenzkunden
SLX-Digitalkonferenz: Zukunftswerkstatt 2024

Mehr Umsatz mit Top-Kontakten

Am 7. Mai erfahren Sie, wie Vertriebsteams Leadgenerierung, Leadnurturing und Leadstrategien effizient steuern können.
Erweiterte Suche
Anmelden
nach oben

2018 | Buch

Introduction Kapitel lesen Erstes Kapitel lesen

High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications

verfasst von: Weitao Li, Fule Li, Prof. Zhihua Wang

Verlag: Springer International Publishing

Buchreihe : Analog Circuits and Signal Processing

Enthalten in: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik"

Einloggen, um Zugang zu erhalten
insite
SUCHEN

Über dieses Buch

This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference.

Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter;

Presents three types of power-efficient architectures of the high-resolution and high-speed AD converter;

Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.

Inhaltsverzeichnis

Frontmatter
Chapter 1. Introduction
Abstract
Applications emerging throughout the years are pushing up requirements of analog-to-digital converter (ADC). To response to new challenges, low power, high speed, and high accuracy have become the important metrics in state-of-the-art designs. This book presents an in-depth analysis on the design of low-power and high-performance ADC and discusses a design case in detail. In this chapter, first, we briefly introduce why ADC interests the industry and academia. Second, we talk about what the book is about. At the end, we make a step to general concepts of ADC.
Weitao Li, Fule Li, Zhihua Wang
Chapter 2. ADC Architecture
Abstract
A successful low-power architecture is extremely important for the high-performance ADC. It helps to save the power dissipation in the systematic level. We focus on the architecture design of the low-power and high-performance ADC in this chapter. First, the traditional architectures, including the flash ADC, the SAR ADC, and the pipelined ADC, are briefly depicted and the limitations are discussed. To try to exceed the limitations, the improvement of the pipelined ADC and the SAR ADC are presented in the following sections. Then to reduce the power dissipation further, two hybrid architectures are discussed. After that, we talk about the time-interleaved ADC. At the end, we sum up the architectures for the low-power and high-performance ADC.
Weitao Li, Fule Li, Zhihua Wang
Chapter 3. Reference Voltage Buffer
Abstract
Reference voltage is a ruler that is used by the ADC to weight the analog input. Accurate reference voltage plays an important role in the high-speed and high-resolution data conversion. In this chapter, we focus on the reference voltage buffer design. First, the traditional narrow-bandwidth buffer and wide-bandwidth buffer are depicted. The narrow-bandwidth one usually needs the large decoupling capacitors, which are difficult to be integrated on chip. The wide-bandwidth one normally consumes the large static current. Second, two reference buffers are introduced to exceed the limitations of the traditional designs. They are the level-shifter-aided reference buffer and the charge-compensation-based reference buffer. As a wide-bandwidth buffer, the level-shifter-aided reference buffer effectively saves the power dissipation. As a narrow-bandwidth buffer, the charge-compensation-based buffer does not need the large decoupling capacitors. At the end, we sum up the buffer designs for the low-power and high-performance ADC.
Weitao Li, Fule Li, Zhihua Wang
Chapter 4. Amplification
Abstract
For the noise-limited ADC, in order to achieve high SNR, the residue amplification is normally required to amplify the conversion residue and improve the accuracy. First, three approaches of residue amplification are presented, and they are opamp-based amplification, comparator-based amplification, and open-loop dynamic amplifier. Since the opamp-based amplification still plays a critical role in the data conversion, we talk about how to provide an opamp for a low-power and high-performance ADC in the following sections. On one hand, we focus on the circuit techniques that assist in relaxing the requirements of the opamp. On the other hand, the opamp design is depicted and a hybrid opamp is introduced in detail. At the end of the chapter, we sum up the residue amplification for the power-efficient and high-performance ADC.
Weitao Li, Fule Li, Zhihua Wang
Chapter 5. Comparator
Abstract
In different architectures introduced throughout the years, the comparator is a necessary circuit block. It plays an important role not only in the accuracy, but also in the speed of the data conversion. In this chapter, we discuss how to provide a comparator for a power-efficient and high-performance ADC. First, the circuit techniques that help to relax the requirements of the comparator are presented. Both the redundancy technique and the reference voltage stabilization technique are described. Second, we make a step to the design considerations of the dynamic comparator, including the speed and power dissipation, the noise, the offset, and the kickback noise. At the end of the chapter, we sum up the comparator design for the power-efficient and high-performance ADC.
Weitao Li, Fule Li, Zhihua Wang
Chapter 6. Calibration
Abstract
Calibration-aided designs are definitely the trend for the state-of-the-art ADCs. They help to improve the performance and save the power of ADCs at low cost. In this chapter, we focus on the calibration techniques for the different ADC architectures. First, the error sources of the pipelined ADC, the SAR ADC, the flash ADC, and the time-interleaved ADC are presented. Second, an overview about the calibration principle is given. Then, we make a step to the calibration schemes of the four architectures. At the end of the chapter, we sum up the calibration techniques of the low-power and high-performance ADC.
Weitao Li, Fule Li, Zhihua Wang
Chapter 7. Design Case
Abstract
A power-efficient 14-bit 150 MSps ADC is presented in this chapter. Range scaling enables a maximal 2-\(\text {V}_{p-p}\) input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multiplying digital-to-analog converter (MDAC) and the second one reduces the total opamp power further. The dedicated sample-and-hold amplifier (SHA) is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the performance. The prototype ADC is fabricated in a 130 nm CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 mW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.
Weitao Li, Fule Li, Zhihua Wang
Chapter 8. Contributions and Future Directions
Abstract
To conclude, we give an introduction to the low-power and high-performance ADC in Chap. 1. In the following chapters, we focus on the state-of-the-art ADCs and design considerations. Successful architecture, circuit block, and calibration make up an ADC. Chapter 2 presents architectures for the ADC. From Chaps. 3, 4 and 5, we illustrate the reference buffer design, the amplification design, and the comparator design. We do not only analyze how to relax the requirements of those circuit blocks in the architecture level, but also depict the modification in the circuit level. The calibration techniques for different architectures are talked about in Chap. 6. By using techniques in the previous chapters, one design case is presented in Chap. 7. In the final chapter, we review the book and look into challenges in the future.
Weitao Li, Fule Li, Zhihua Wang
Backmatter
Metadaten
Titel
High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications
verfasst von
Weitao Li
Fule Li
Prof. Zhihua Wang
Copyright-Jahr
2018
Electronic ISBN
978-3-319-62012-1
Print ISBN
978-3-319-62011-4
DOI
https://doi.org/10.1007/978-3-319-62012-1

Neuer Inhalt

    Bildnachweise