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This book describes techniques for realizing wide bandwidth (125MHz) over-sampled analog-to-digital converters (ADCs) in nano meter-CMOS processes. The authors offer a clear and complete picture of system level challenges and practical design solutions in high-speed Delta-Sigma modulators. Readers will be enabled to implement ADCs as continuous-time delta-sigma (CT∆Σ) modulators, offering simple resistive inputs, which do not require the use of power-hungry input buffers, as well as offering inherent anti-aliasing, which simplifies system integration. The authors focus on the design of high speed and wide-bandwidth ΔΣMs that make a step in bandwidth range which was previously only possible with Nyquist converters. More specifically, this book describes the stability, power efficiency and linearity limits of ΔΣMs, aiming at a GHz sampling frequency.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Introduction

Abstract
Analog-to-digital converter developments are driven by the increasing demand for signal bandwidth and dynamic range in applications such as medical imaging, high-definition video processing and, in particular, wireline and wireless communications. Figure 1.1 shows a block diagram of a basic wireless receiver. It has three main building blocks: an RF front-end, an analog-to-digital converter (ADC) and a digital baseband processor. The role of the RF front-end is to filter, amplify the signals present at the antenna input and down-convert them to baseband. The ADC samples and digitizes the analog signals at the output of the RF front-end and outputs the results to the baseband processor. To achieve high data rates, wireless standards rely on advanced digital modulation techniques that can be advantageously implemented in baseband processors fabricated in nanometer-CMOS, which also motivates the development of ADCs in these technologies.
Muhammed Bolatkale, Lucien J. Breems, Kofi A. A. Makinwa

Chapter 2. Continuous-Time Delta-Sigma Modulator

Abstract
This chapter starts with a brief explanation of the operation of an ideal single-loop continuous-time delta-sigma (CTΔΣ) modulator and describes its major building blocks, i.e. the loop filter, quantizer and digital-to-analog converter (DAC). In Sect. 2.2, we introduce the system-level non-idealities that limit the performance of such a modulator. Finally, we will illustrate the effect of system-level non-idealities on the key performance metrics of the modulator: its signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), and sampling speed (f s ).
Muhammed Bolatkale, Lucien J. Breems, Kofi A. A. Makinwa

Chapter 3. Continuous-Time Delta-Sigma Modulators at High Sampling Rates

Abstract
This chapter describes the design of a continuous-time delta-sigma (CTΔΣ) modulator that can achieve a 125 MHz signal bandwidth (BW) with a 70 dB dynamic range (DR) in 45 nm CMOS. As explained in the previous chapter, various system-level non-idealities (noise, non-linearity, metastability and excess loop delay (ELD)), will limit its performance. Especially for a modulator which targets a wide bandwidth, these limitations pose a major challenge.
Muhammed Bolatkale, Lucien J. Breems, Kofi A. A. Makinwa

Chapter 4. A 4 GHz Continuous-Time ΔΣ ADC

Abstract
In this chapter, the implementation of a 4 GHz continuous-time delta-sigma (CTΔΣ) ADC is presented that uses the high-speed filter topology proposed in Chap. 3. The ADC is fabricated in a 45 nm LP-CMOS with a supply voltage of 1.1 V with a target power dissipation of 400 mW. The low supply voltage requires cascaded stages to make gain in blocks such as an OTA and a quantizer. The ADC employs a 3rd order loop filter architecture with high-speed capacitive feedforward summation node. The ADC is sampled at 4 GHz and uses a 4-bit quantizer which is designed for latency less than half a clock delay.
Muhammed Bolatkale, Lucien J. Breems, Kofi A. A. Makinwa

Chapter 5. A 2 GHz Continuous-Time ΔΣ ADC with Dynamic Error Correction

Abstract
In the previous chapter, we have presented the design and implementation details of a 3rd order 4-bit continuous-time delta-sigma (CTΔΣ) ADC which uses a high-speed filter topology. However, its signal-to-noise ratio (SNR) and signal-to-noise-and-distortion ratio (SNDR) are limited to 65.5 and 65 dB at −0.5 dBFS input, respectively. The main reason for this is that for large input signals, the non-linearity of the 4-bit feedback DAC (DAC1) causes harmonic components and quantization noise to fold into the signal band, which increases the in-band noise. In order to improve the SNR and SNDR of the modulator, the non-linearity of the multi-bit DAC1 must be tackled. This chapter discusses how to do this, and in particular, how to improve the high frequency linearity of DAC1 without degrading the stability of the modulator.
Muhammed Bolatkale, Lucien J. Breems, Kofi A. A. Makinwa

Chapter 6. Conclusions

Abstract
This work experimentally demonstrates the feasibility and design of a wide-band, high-dynamic range oversampled analog-to-digital converter (ADC) that can reach a performance comparable to Nyquist ADCs.
Muhammed Bolatkale, Lucien J. Breems, Kofi A. A. Makinwa

Backmatter

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