01.12.2018  Research  Ausgabe 1/2018 Open Access
Highspeed hardware architecture for implementations of multivariate signature generations on FPGAs
1 Introduction
2 Method
Signature scheme  Finite field  Message  Signature  Central map transformation 
L
_{1}
transformation 
L
_{2}
transformation 

enTTS (20,28)  GF((2^{4})^{2})  y_{0}, y_{1}, …, y_{19}  x_{0}, x_{1}, …, x_{27} 
\( {\displaystyle \begin{array}{l}F\left({\overline{x}}_0,{\overline{x}}_1,\dots, {\overline{x}}_{27}\right)=\\ {}\left({f}_0,{f}_1,\dots, {f}_{19}\right).\end{array}} \)

\( \overline{y}= Ay+B \)

\( x=C\overline{x}+D \)

3 A highspeed hardware architecture for multivariate signature
3.1 Overview of the hardware architecture
3.2 Performance evaluation of irreducible polynomial in composite fields
3.3 Finite field adder
3.4 Finite field multiplier
3.5 Multiplicative inverter
3.6 Parallel GaussJordan eliminator
4 Results
Signature scheme  Message size  Signature size  L_{1} matrix  L_{2} matrix  Systems of linear equations  Clock cycle  Time frequency  Executing time 

enTTS(20,28)  20 B  28 B  20 × 20  28 × 28  9 × 9  90  100 MHz  0.9 μs 