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Über dieses Buch

This book is based on the 18 tutorials presented during the 26th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, with specific contributions focusing on hybrid ADCs, smart sensors for the IoT, sub-1V and advanced-node analog circuit design. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.



Part I


Chapter 1. Hybrid Data Converters

This work illustrates the broad and multidimensional nature of hybrid converters which reflects an optimal design policy going beyond the limiting boundaries of “the combination of known architectures” and the analog to digital converter itself. The analog to digital conversion extends from waves at the antenna interface to digital bits at the digital processor. This conversion is conditioned to the properties of CMOS technology through optimal combinations of techniques across multiple signal domains and hardware abstraction layers using modulation, redundancy, scheduling, on-chip information and other concepts. Dependent on the speed resolution domain, hybrid architectures take a different shape that matches to thermal noise or process technology limitations dominating in the corresponding domain.
Kostas Doris

Chapter 2. Hybrid and Segmented ADC Techniques to Optimize Power Efficiency and Area: The Case of a 0.076 mm2 600 MS/s 12b SAR-ΔΣ ADC

An example of usage of ADC hybrid techniques and DAC segmented topologies to achieve high power efficiency and low total area is presented. The resulting hybrid ADC architecture consisting of a coarse SAR ADC followed by an incremental ΔΣ fine converter provides better suppression of thermal noise added during conversion for a given power compared to a conventional SAR. The usage of a segmented charge-sharing charge-redistribution DAC scheme enables significant area saving compared to conventional DAC topologies. The 28 nm 600 MS/s four-way interleaved prototype ADC achieves an SNDR of 60.7 dB and 58 dB at low and high frequency, respectively, while consuming only 26 mW for a total area of 0.076 mm2.
Alessandro Venca, Nicola Ghittori, Alessandro Bosi, Claudio Nani

Chapter 3. Interleaved Pipelined SAR ADCs: Combined Power for Efficient Accurate High-Speed Conversion

High-speed mobile data communication requires low-power, high-speed ADCs with medium to high resolutions. This paper discusses how the combination of pipelining, SAR, and time interleaving can realize highly efficient Nyquist ADCs with large bandwidths and high accuracies. The trade-offs of the architecture are described as well as the design challenges of the different building blocks and their impact on the overall ADC performance. Finally, some design examples are discussed.
Ewout Martens

Chapter 4. Hybrid VCO Based 0-1 MASH and Hybrid ΔΣ SAR

Two hybrid, highly digital \(\Delta \Sigma \) ADCs are presented in this work. A SAR + VCO 0-1 MASH architecture is used for a 12-bit scaling friendly ADC which does not require VCO nonlinearity correction. PVT sensitivity of VCO tuning gain is canceled by using a digital, background calibration technique. A 40 nm CMOS prototype achieves 74.3 dB SNDR while operating at 36 MS/s from 1.1 V supply. The prototype exhibits a Schreier FoM of 171 dB. A hybrid SAR \(\Delta \Sigma \) ADC is presented which uses a passive integrator to achieve first-order noise shaping. The proposed noise-shaping SAR has very high immunity against PVT variations and does not require any calibration. Fabricated in an 130 nm CMOS process, the noise-shaping SAR ADC achieves an SNDR of 74 dB while operating at 2 MS/s from 1.2 V supply. The Schreier FoM for the noise-shaping SAR is 167 dB.
Arindam Sanyal, Wenjuan Guo, Nan Sun

Chapter 5. A Hybrid Architecture for a Reconfigurable SAR ADC

While conventional flash, pipelined, successive-approximation-register (SAR), and ΔΣ analog-to-digital converters (ADCs) have demonstrated a fundamental trade-off between speed and resolution, a recent trend of hybrid ADCs nicely blends different architectures into one ADC design, enabling new breakthroughs in resolution, speed, area, and power efficiency. The mixture of multiple ADC architectures also opens up a new possibility to configure an ADC across a wide speed and resolution range. This paper introduces a SAR-based hybrid design incorporating with a hybrid DAC linearization scheme to extend the application of a power-efficient SAR ADC for high-resolution sensor readout interfaces. This architecture allows an ADC to be configured between SAR- and ΔΣ-type performance with flexible sampling rate and is especially suitable for various Internet of Things (IoT) sensor applications.
Yun-Shiang Shu, Liang-Ting Kuo, Tien-Yu Lo

Chapter 6. A Hybrid ADC for High Resolution: The Zoom ADC

This paper presents a dynamic zoom ADC for audio applications. It achieves 109-dB DR, 106-dB SNR, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating 1.12 mW and occupying only 0.16 mm2 in 0.16-μm CMOS. This translates to state-of-the-art energy and area efficiency. In this paper, the system- and circuit-level design of the ADC will be presented.
Burak Gönen, Fabio Sebastiano, Robert van Veldhoven, Kofi A. A. Makinwa

Part II


Chapter 7. Advances in Biomedical Sensor Systems for Wearable Health

This book chapter will discuss advancements in analog circuit design specifically for various wearable healthcare applications. There are a number of general trends that can be observed in this field, like multimodal sensing applications, which will be discussed. There will be a focus on analog circuits for some of the most relevant signal modalities including ExG, bio-impedance, and photoplethysmogram (PPG). Common circuit topologies and some recent state-of-the-art implementations for those will be discussed.
Nick Van Helleputte, Jiawei Xu, Hyunsoo Ha, Roland Van Wegberg, Shuang Song, Stefano Stanzione, Samira Zaliasl, Richard van den Hoven, Wenting Qiu, Haoming Xin, Chris Van Hoof, Mario Konijnenburg

Chapter 8. An Ultra-low Power, Robust Photoplethysmographic Readout Exploiting Compressive Sampling, Artifact Reduction, and Sensor Fusion

This paper describes an ultra-low power yet robust photoplethysmographic (PPG) readout exploiting various mixed-signal processing techniques. Firstly, compressive sampling (CS) enables to reduce the LED driver power consumption by up to 30x. Feature extraction is performed in the compressed domain, using a Lomb-Scargle periodogram (LSP) to extract the average heart rate and variability, without requiring complex signal reconstruction techniques. Secondly, we demonstrate, in simulations, increased robustness through digital motion artifact reduction for PPG signals, using a spectral subtraction technique. Finally, simulations show further signal enhancement through sensor fusion, enabling electrocardiogram (ECG)-assisted PPG acquisition for cuffless blood pressure (BP) monitoring. The power consumption gains of compressive sampling and feature extraction directly from the compressed domain are demonstrated through a 172 μW compressive sampling PPG acquisition ASIC fabricated in a 0.18 μm CMOS process. The ASIC achieves up to 30x reduction in LED driver power consumption while extracting heart rate with an accuracy conforming to ANSI-AAMI standards.
Venkata Rajesh Pamula, Chris Van Hoof, Marian Verhelst

Chapter 9. A 32 kHz DTCXO RTC Module with an Overall Accuracy of ±1 ppm and an All-Digital 0.1 ppm Compensation-Resolution Scheme

This paper presents an ultralow power (240 nA), wide voltage range (1.25–5.5 V), temperature-compensated RTC module achieving a typical accuracy of ±1 ppm at 1 Hz over the industrial temperature range of −40 to 85 °C. This is obtained by combining a miniature tuning fork 32 kHz XTALs with an ASIC in a miniature 8-pin ceramic package measuring only 3.2×1.5×0.8 mm3. An innovative patented all-digital interpolation scheme allows the accurate generation of a one pulse per second (1 PPS) signal with a resolution of 0.1 ppm permitting significant savings in terms of both the circuit area and power consumption (4×) compared to previously available such products.
David Ruffieux, Nicola Scolari, Frédéric Giroud, Franz Pengg, Daniel Severac, Thanh Le, Silvio Dalla Piazza, Olivier Aubry

Chapter 10. Energy-Efficient High-Resolution Resistor-Based Temperature Sensors

This paper presents two high-resolution CMOS temperature sensors intended for the temperature compensation of MEMS/quartz frequency references. One is based on a Wien bridge RC filter, which outputs a temperature-dependent phase shift when driven by a stable frequency; the other is based on a Wheatstone bridge, which outputs a temperature-dependent current. The bridge outputs are digitized by energy-efficient continuous-time delta-sigma modulators. Two prototypes were fabricated in a standard 0.18 μm CMOS technology. Both dissipate less than 200 μW and achieve sub-mK resolution, as well as sub-0.2pJ·K2 resolution FoMs, which corresponds to state-of-the-art energy efficiency.
Sining Pan, Kofi A. A. Makinwa

Chapter 11. A High-Resolution Self-Oscillating Integrating Dual-Slope CDC for MEMS Sensors

An integrating dual-slope (DS) capacitance-to-digital converter (CDC), specifically designed for interfacing capacitive MEMS sensors, is presented. In particular, this work proposes a CDC that interfaces a MEMS sensor built with a bridge of capacitors. In this bridge, some capacitances are pressure sensitive, causing pressure-related changes in the bridge output. The voltage to digital conversion is then realized in two steps. First, a voltage amplifier boosts the output of the bridge. Second, an integrating DS ADC digitizes the output of the amplifier. The proposed ADC uses time instead of amplitude resolution to generate a multi-bit digital output stream. In addition, it performs noise shaping of the quantization error to reduce measurement time. These characteristics lead to the following properties: intrinsically low sensitivity to temperature and process variations, simplicity of trimming offset and gain to correct for sensor parameter spread, and an energy-efficient implementation. The effectiveness of the proposed architecture is demonstrated by measurements performed on a prototype, designed, and fabricated using standard 0.13 μm CMOS technology. Experimental results show that the proposed CDC achieves a maximum resolution of 17 bits, which corresponds to a capacitive resolution of 5.4aF, while consuming only 146 μA from a 1.5 V power supply, with an effective area of 0.317mm2.
J. P. Sanjurjo, Enrique Prefasi, C. Buffa, C. Rogi, R. Gaggl

Chapter 12. Ultra-low Power Charge-Pump-Based Bandgap References

This paper presents a 48 nW, − 60 dB PSRR@ DC, switched capacitor bandgap reference circuit operational from 500 mV V DD . The design uses a switched capacitor network for the architecture, where instead of resistors, switching capacitors are used for generating the reference. A charge-pump network is used to reduce the minimum V DD required to operate the circuit. Compared to the prior work, this design improves the PSRR well over − 60 dB by using current source architecture. Measurement result shows a 1 mV change in output voltage for a 4.9 V change in V DD for a high-voltage version of the design. It achieves a stability of 45 ppm/C at an output voltage of 500 mV. We also present the theoretical background of the charge-pump-based bandgap while reviewing prior low-voltage bandgap circuits.
Shikhar Tewari, Aatmesh Shrivastava

Part III


Chapter 13. FDSOI Technology, Advantages for Analog/RF and Mixed-Signal Designs

Fully depleted silicon on insulator (FDSOI) is one of the technology alternatives that permits today to follow CMOS More Moore law for the 28 nm node and beyond, while still dealing with fully planar transistors. A large number of publications have presented over the last years the benefits of this technology for energy-efficient integration of digital signal processing cores. This paper will focus on the benefits of FDSOI technology for analog/RF/millimeter-wave and high-speed mixed-signal circuits, by taking full advantage of ultra-wide voltage range body biasing tuning. For each category of circuits (analog/RF and mmW), concrete design examples are given in order to highlight the main design features specific to FDSOI.
Andreia Cathelin

Chapter 14. Analog/Mixed-Signal Design in FinFET Technologies

Consumer demand for low-power mobile ICs has propelled CMOS scaling to arrive at the fully depleted finFET with foundry offerings already available at 16/14, 10, and 7 nm. The compact three-dimensional structure of the finFET offers superior short-channel control that achieves digital power reduction while increasing device performance for a given area. As system-on-chip technology remains driven by logic and SRAM scaling needs, designers of analog/mixed-signal subsystems must continue to adapt to new technology constraints. We attempt to summarize the challenges and technology considerations encountered when we port analog/mixed-signal designs to a finFET node. At 16/14 nm and beyond, designers also face many implications from scaling innovations leading to the finFET.
Alvin L. S. Loke, Esin Terzioglu, Albert A. Kumar, Tin Tin Wee, Kern Rim, Da Yang, Bo Yu, Lixin Ge, Li Sun, Jonathan L. Holland, Chulkyu Lee, Deqiang Song, Sam Yang, John Zhu, Jihong Choi, Hasnain Lakdawala, Zhiqin Chen, Wilson J. Chen, Sreeker Dundigal, Stephen R. Knol, Chiew-Guan Tan, Stanley S. C. Song, Hai Dang, Patrick G. Drennan, Jun Yuan, P. R. Chidambaram, Reza Jalilizeinali, Steven J. Dillen, Xiaohua Kong, Burton M. Leary

Chapter 15. Analog Circuits in 28 nm and 14 nm FinFET

Intel Tri-Gate transistors (FinFET) further shrink MOSFET technologies and have been a disruptive semiconductor innovation offering lower area, lower supply voltage, and lower power consumption. This paper presents and compares measurements and designs implemented in the 14 nm FinFET and in a planar 28 nm technology. The impact of these novel devices and their characteristics on the overall performance of analog circuits are shown.
Lukas Dörrer, Franz Kuttner, Francesco Conzatti, Patrick Torta

Chapter 16. Pipeline and SAR ADCs for Advanced Nodes

The switched-capacitor SAR architecture has benefited tremendously from technology scaling. We first present a charge-injection-based SAR architecture that shrinks the die area needed for a SAR ADC and achieves outstanding energy efficiency. We go on to discuss pipeline ADCs using SAR sub-ADCs and a ring amplifier. We present a SAR- assisted pipeline that achieves record efficiency for >12-bit pipeline ADCs. We argue that SAR ADCs are among the most efficient stand-alone converters for advanced nodes and an important building block for other converters.
Michael P. Flynn, Kyojin Choo, Yong Lim

Chapter 17. Time-Based Biomedical Readout in Ultra-Low-Voltage, Small-Scale CMOS Technology

Personalized healthcare solutions are pushing the boundaries for low-power and low-cost sensor readout devices. However, achieving this requirement requires a trade-off between cost, power consumption and accuracy or the dynamic range capability of these devices. In this paper, we outline the main reasons for this trade-off and present existing solutions in literature. In specific, we identify time-domain operation as one of the promising techniques to overcome this trade-off. We present the state-of-art architectures based on time-based operation and discuss their challenges in designing for low-power, low-cost biomedical sensor readout. Furthermore, we propose and discuss a time-based readout design that can overcome these challenges.
Rachit Mohan, Samira Zaliasl, Chris Van Hoof, Nick Van Helleputte

Chapter 18. A 4.4mW-TX, 3.6 mW-RX Fully Integrated Bluetooth Low Energy Transceiver for IoT Applications

We present an ultra-low-power Bluetooth Low Energy (BLE) transceiver for Internet of things (IoT) optimized for 28-nm CMOS. A transmitter (TX) employs an all-digital phase-locked loop (ADPLL) with switched current source digitally controlled oscillator (DCO) and class-E/F2 power amplifier. The proposed oscillator combines the benefits of low-supply voltage operation of conventional NMOS cross-coupled oscillators with high current efficiency of the complementary push-pull oscillators. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO modulation. The switching power amplifier operates in class-E/F2 to maximally enhance its efficiency at low output power. The receiver (RX) operates in discrete time (DT) at high sampling rate ( ∼ 10 GSample/sec) with an intermediate frequency (IF) placed beyond 1/f noise corner of MOS devices. Multistage multi-rate charge-sharing (CS) band-pass filters (BPF) are placed to achieve high out-of-band linearity, low noise, and low power consumption. Furthermore, an integrated on-chip matching network serves both PA and LNTA, thus allowing a one-pin direct antenna connection with no extra band selection filters. The transceiver consumes 2.75 mW in RX and 3.7 mW in TX when delivering 0 dBm in BLE.
Masoud Babaie, Sandro Binsfeld Ferreira, Feng-Wei Kuo, Robert Bogdan Staszewski
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