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Erschienen in:
Hybrid Data Converters Kapitel lesen Erstes Kapitel lesen

2018 | OriginalPaper | Buchkapitel

4. Hybrid VCO Based 0-1 MASH and Hybrid ΔΣ SAR

verfasst von : Arindam Sanyal, Wenjuan Guo, Nan Sun

Erschienen in: Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog Circuit Design

Verlag: Springer International Publishing

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Abstract

Two hybrid, highly digital \(\Delta \Sigma \) ADCs are presented in this work. A SAR + VCO 0-1 MASH architecture is used for a 12-bit scaling friendly ADC which does not require VCO nonlinearity correction. PVT sensitivity of VCO tuning gain is canceled by using a digital, background calibration technique. A 40 nm CMOS prototype achieves 74.3 dB SNDR while operating at 36 MS/s from 1.1 V supply. The prototype exhibits a Schreier FoM of 171 dB. A hybrid SAR \(\Delta \Sigma \) ADC is presented which uses a passive integrator to achieve first-order noise shaping. The proposed noise-shaping SAR has very high immunity against PVT variations and does not require any calibration. Fabricated in an 130 nm CMOS process, the noise-shaping SAR ADC achieves an SNDR of 74 dB while operating at 2 MS/s from 1.2 V supply. The Schreier FoM for the noise-shaping SAR is 167 dB.

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Vorheriges Kapitel Interleaved Pipelined SAR ADCs: Combined Power for Efficient Accurate High-Speed Conversion
Nächstes Kapitel A Hybrid Architecture for a Reconfigurable SAR ADC
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Metadaten
Titel
Hybrid VCO Based 0-1 MASH and Hybrid ΔΣ SAR
verfasst von
Arindam Sanyal
Wenjuan Guo
Nan Sun
Copyright-Jahr
2018
Buch
Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog Circuit Design

Print ISBN: 978-3-319-61284-3

Electronic ISBN: 978-3-319-61285-0

Copyright-Jahr: 2018

DOI
https://doi.org/10.1007/978-3-319-61285-0_4

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