Weitere Kapitel dieses Buchs durch Wischen aufrufen
Due to their flexible architecture, lower-cost and faster processing, Field Programmable Gate Array (FPGA) presents one of the stimulating choices for implementing modern embedded systems. This is due to their intrinsic parallelism, fast processing speed, rising integration scale and lower-cost solution. This kind of platforms can be considered as a futuristic implementation platform. The growing configurable logic capacity of FPGA has enabled designers to incorporate one or more processors in FPGA platform. In contrast to the traditional hard cores, the soft cores processors present an interesting solutions for implementing embedded applications. They give designers the ability to adapt many configurations to their specific application; including memory subsystems, interrupt handling, ISA features, etc. Faced to the various problems related to the selection of an efficient soft-core FPGA embedded processor with appropriate configuration, co-design methodology presents a good deal for embedded designers. The most crucial step in the design of embedded systems is the hardware/software partitioning. This step consists of deciding which component is suitable for hardware implementation and which one is more appropriate for software implementation. This research field is especially active (always on the move) and several approaches are proposed. In this chapter, we will present our contribution on the hardware/software partitioning co-design approach, and discuss their involvement on design acceleration and architecture performances. The first part of this chapter describes the effect of the MicroBlaze Xilinx configuration on the embedded system performance. The second part introduces our new hardware/software partitioning approach on a complex secure lightweight cryptographic algorithm. This work can contribute to enforce the security of SCADA (Supervision Control and Data Acquisition) systems and the DSS (Digital Signal Standard) without compromising the cost and the performance of the final system.
Bitte loggen Sie sich ein, um Zugang zu diesem Inhalt zu erhalten
Sie möchten Zugang zu diesem Inhalt erhalten? Dann informieren Sie sich jetzt über unsere Produkte:
Arulmozhiyal, R. (2012). Design and implementation of fuzzy PID controller for BLDC motor using FPGA. In IEEE International Conference on Power Electronics, Drives and Energy Systems ( PEDES) (pp. 1–6), December 16–19, 2012. doi: 10.1109/pedes.2012.6484251.
Bolado, M., Posadas, H., Castillo, J., Huerta, P., Sanchez, P., Sanchez, C., Fouren, H., & Blasco, F. (2004). Platform based on open-source cores for industrial applications. In Europe Conference and Exhibition on Design, Automation and Test (pp. 1014–1019), February 16–20, 2004. doi: 10.1109/date.2004.1269026.
Boßung, W., Huss, S. A., & Klaus, S. (1999). High-level embedded system specifications based on process activation conditions. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 21(3), 277–291. CrossRef
Chatha, K. S., & Vemuri, R. (2000). An iterative algorithm for hardware-software partitioning, hardware design space exploration and scheduling. Design Automation for Embedded Systems, 5(3–4), 281–293. CrossRef
Cherif, S., Quadri, I. R., Meftali, S., & Dekeyser, J. (2010). Modeling reconfigurable systems-on-chips with UML MARTE profile: An exploratory analysis. In 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools ( DSD) (pp. 706–713), September 1–3, 2010. doi: 10.1109/dsd.2010.58.
Cloute, F., Contensou, J. N., Esteve, D., Pampagnin, P., Pons, P., & Favard, Y. (1999). Hardware/software co-design of an avionics communication protocol interface system: An industrial case study. In 7th International Workshop on Hardware/Software Codesign ( CODES ’99) (pp. 48–52). doi: 10.1109/hsc.1999.777390.
Dave, N., Ng, M. C., & Arvind. (2005). Automatic synthesis of cache-coherence protocol processors using Bluespec. In 3rd ACM and IEEE International Conference on Formal Methods and Models for Co-Design (pp. 25–34), July 11–14, 2005. doi: 10.1109/memcod.2005.1487887.
De Michell, G., & Gupta, R. K. (1997). Hardware/software co-design. Proceedings of the IEEE, 85(3), 349–365. CrossRef
Denning, D., Irvine, J., Stark, D., & Delvin, M. (2004). Multi-user FPGA co-simulation over TCP/IP. In 15th IEEE International Workshop on Rapid System Prototyping (pp. 151–156), June 28–30, 2004. doi: 10.1109/iwrsp.2004.1311110.
Feng, W., Yuan, X., & Takach, A. (2009). Variation-aware resource sharing and binding in behavioral synthesis. In Asia and South Pacific Design Automation Conference ( ASP- DAC) (pp. 79–84), January 19–22, 2009. doi: 10.1109/aspdac.2009.4796445.
Fujita, M., & Nakamura, H. (2001). The standard SpecC language. In Proceedings of the 14th International Symposium on Systems synthesis (pp. 81–86).
Gruian, F., & Westmijze, M. (2008). VHDL vs. Bluespec system verilog: A case study on a java embedded architecture. In Proceedings of the 2008 ACM Symposium on Applied Computing (pp. 1492–1497).
Gupta, R. K., Coelho, C. N., & De Micheli, G. (1992). Synthesis and simulation of digital systems containing interacting hardware and software components. In 29th ACM/IEEE Design Automation Conference (pp. 225–230), June 8–12, 1992. doi: 10.1109/dac.1992.227832.
Henkel, J., & Ernst, R. (1998). High-level estimation techniques for usage in hardware/software co-design. In Asia and South Pacific Design Automation Conference (pp. 353–360), February 10–13, 1998. doi: 10.1109/aspdac.1998.669500.
Ismail, T. B., Abid, M., O’brien, K., & Jerraya, A. (1994). An approach for hardware-software codesign. In 5th International Workshop on Rapid System Prototyping Shortening the Path from Specification to Prototype (pp. 73–80), June 21–23, 1994. doi: 10.1109/iwrsp.1994.315907.
Jianzhuang, W., Youping, C., Jingming, X., Bing, C., & Haiping, L. (2008). System structure for FPGA-based SOPC design using hard tasks. In 6th IEEE International Conference on Industrial Informatics, INDIN 2008 (pp. 1154–1159), July 13–16, 2008. doi: 10.1109/indin.2008.4618277.
Jing-Jie, W., & Rui, H. (2011). A FPGA-based wireless security system. In Third International Conference on Multimedia Information Networking and Security ( MINES) (pp. 512–515), November 4–6, 2011. doi: 10.1109/mines.2011.82.
Joven, J., Strict, P., Castells-Rufas, D., Bagdia, A., De Micheli, G., & Carrabina, J. (2011). HW-SW implementation of a decoupled FPU for arm-based cortex-M1 SOCS in FPGAS. In 6th IEEE International Symposium on Industrial Embedded Systems ( SIES) (pp. 1–8), June 15–17, 2011. doi: 10.1109/sies.2011.5953649.
Kalavade, A., & Lee, E. A. (1994). A global criticality/local phase driven algorithm for the constrained hardware/software partitioning problem. In 3rd International Workshop on Hardware/Software Codesign (pp. 42–48), September 22–24, 1994. doi: 10.1109/hsc.1994.336724.
Kalomiros, J. A., & Lygouras, J. (2008). Design and evaluation of a hardware/software FPGA-based system for fast image processing. Microprocessors and Microsystems, 32(2), 95–106. CrossRef
Kikuchi, H., & Morioka, K. (2012). Development of wireless image sensor nodes based on FPGA for human tracking in intelligent space. In IECON 2012— 38th Annual Conference on IEEE Industrial Electronics Society (pp. 5529–5534), October 25–28, 2012. doi: 10.1109/iecon.2012.6388950.
Korb, M., & Noll, T. G. (2010). LDPC decoder area, timing, and energy models for early quantitative hardware cost estimates. In International Symposium on System on Chip ( SoC) (pp. 169–172), September 29–30, 2010. doi: 10.1109/issoc.2010.5625546.
Ku, D. C., & De Mitcheli, G. (1992). Relative scheduling under timing constraints: Algorithms for high-level synthesis of digital circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(6), 696–718. CrossRef
Lach, J., Mangione-Smith, W. H., & Potkonjak, M. (1999). Robust FPGA intellectual property protection through multiple small watermarks. In Proceedings 36th Design Automation Conference (pp. 831–836), 1999.
Li, Y.-T. S., & Malik, S. (1995). Performance analysis of embedded software using implicit path enumeration. ACM SIGPLAN Notices, 30(11), 88–98. CrossRef
Lingbo, Z., Fuchun, S., & Zengqi, S. (2006). Cloud model-based controller design for flexible-link manipulators. In IEEE Conference on Robotics, Automation and Mechatronics (pp. 1–5), December 2006. doi: 10.1109/ramech.2006.252742.
López-Vallejo, M., & López, J. C. (2003). On the hardware-software partitioning problem: System modeling and partitioning techniques. ACM Transactions on Design Automation of Electronic Systems (TODAES), 8(3), 269–297. CrossRef
Lysecky, R., & Vahid, F. (2004). A configurable logic architecture for dynamic hardware/software partitioning. In Design, Automation and Test in Europe Conference and Exhibition (pp. 480-485), February 16–20, 2004. doi: 10.1109/date.2004.1268892.
Madsen, J., Grode, J., Knudsen, P. V., Petersen, M. E., & Haxthausen, A. (1997). LYCOS: The Lyngby co-synthesis system. Design Automation for Embedded Systems, 2(2), 195–235. CrossRef
Mcloone, M., & Mccanny, J. V. (2003). Generic architecture and semiconductor intellectual property cores for advanced encryption standard cryptography. IEE Proceedings on Computers and Digital Techniques, 150(4), 239–244. CrossRef
Monmasson, E., & Cirstea, M. N. (2007). FPGA design methodology for industrial control systems—A review. IEEE Transactions on Industrial Electronics, 54(4), 1824–1842. CrossRef
Mysore, N., Akcakaya, M., Bajcsy, J., & Kobayashi, H. (2005). A new performance evaluation technique for iteratively decoded magnetic recording systems. In Digests of the IEEE International Magnetics Conference ( INTERMAG) (pp. 1603–1604), April 4–8, 2005. doi: 10.1109/intmag.2005.1464235.
Nasreddine, N., Boizard, J. L., Escriba, C., & Fourniols, J. Y. (2010). Wireless sensors networks emulator implemented on a FPGA. In International Conference on Field-Programmable Technology ( FPT) (pp. 279–282), December 8–10, 2010. doi: 10.1109/fpt.2010.5681484.
Noonburg, D. B., & Shen, J. P. (1997). A framework for statistical modeling of superscalar processor performance. In 3rd International Symposium on High-Performance Computer Architecture (pp. 298–309), February 1–5, 1997. doi: 10.1109/hpca.1997.569691.
Reynari, L. M., Cucinotta, F., Serra, A., & Lavagno, L. (2001). A hardware/software co-design flow and IP library based of simulink. In Design Automation Conference (pp. 593–598), 2001. doi: 10.1109/dac.2001.156209.
Samarawickrama, M., Rodrigo, R., & Pasqual, A. (2010). HLS approach in designing FPGA-based custom coprocessor for image preprocessing. In 5th International Conference on Information and Automation for Sustainability ( ICIAFs) (pp. 167–171), December 17–19, 2010. doi: 10.1109/iciafs.2010.5715654.
Sorin, D. J., Pai, V. S., Adve, S. V., Vemon, M. K., & Wood, D. A. (1998). Analytic evaluation of shared-memory systems with ILP processors. In The 25th Annual International Symposium on Computer Architecture (pp. 380–391), June 27–July 1, 1998. doi: 10.1109/isca.1998.694797.
Stitt, G., Lysecky, R., & Vahid, F. (2003). Dynamic hardware/software partitioning: A first approach. In Proceedings of the 40th Annual Design Automation Conference (pp. 250–255).
Stoy, E., & Zebo, P. (1994). A design representation for hardware/software co-synthesis. In The 20th EUROMICRO Conference on System Architecture and Integration (pp. 192–199), September 5–8, 1994. doi: 10.1109/eurmic.1994.390391.
Talpin, J., Le Guernic, P., Shukla, S. K., Gupta, R., & Doucet, F. (2003). Polychrony for formal refinement-checking in a system-level design methodology. In 3rd International Conference on Application of Concurrency to System Design (pp. 9–19), June 18–20, 2003. doi: 10.1109/csd.2003.1207695.
Thangavelu, A., Varghese, M. V., & Vaidyan, M. V. (2012). Novel FPGA based controller design platform for DC–DC buck converter using HDL co-simulator and Xilinx system generator. In IEEE Symposium on Industrial Electronics and Applications ( ISIEA) (pp. 270–274), September 23–26, 2012. doi: 10.1109/isiea.2012.6496642.
Wakabayashi, K., & Okamoto, T. (2000). C-based SoC design flow and EDA tools: An ASIC and system vendor perspective. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(12), 1507–1522. CrossRef
Washington, C., & Dolman, J. (2010). Creating next generation HIL simulators with FPGA technology. In IEEE AUTOTESTCON (pp. 1–6), September 13–16, 2010. doi: 10.1109/autest.2010.5613618.
Wiangtong, T., Cheung, P. Y., & Luk, W. (2005). Hardware/software code sign: A systematic approach targeting data-intensive applications. IEEE Signal Processing Magazine, 22(3), 14–22. CrossRef
Wolf W. (2003). A decade of hardware/software codesign. Computer, 36(4), 38–43.
Xiaoyin, S., & Dong, S. (2007). Development of a new robot controller architecture with FPGA-based IC design for improved high-speed performance. Industrial Informatics, IEEE Transactions on, 3(4), 312–321. CrossRef
- Impact of Hardware/Software Partitioning and MicroBlaze FPGA Configurations on the Embedded Systems Performances
Slim Ben Othman
Slim Ben Saoud
Neuer Inhalt/© ITandMEDIA, Best Practices für die Mitarbeiter-Partizipation in der Produktentwicklung/© astrosystem | stock.adobe.com