Impact of interfacial layer using ultra-thin SiO₂ on electrical and structural characteristics of Gd₂O₃ MOS capacitor

The aim of present study is to improve the quality of Gd₂O₃/p-Si MOS structure by reducing interface trap charge density. Therefore, the ultra-thin SiO₂ layer was grown to high-k/Si interface. The effect of the post deposition annealing on the structural properties of the Gd₂O₃/SiO₂ films and electrical characteristics of the Al/Gd₂O₃/SiO₂/p-Si/Al were investigated for three different temperature. Besides, the effect of the series resistance and measurement frequency on the electrical characteristics of the p-MOS capacitors was examined in detail. 118 nm-thick Gd₂O₃ films were grown by RF magnetron sputtering following the 5 nm-thick SiO₂ deposition on p type Si wafer by dry oxidation method. While the Gd₂O₃ monoclinic characteristic peaks were observed in the Gd₂O₃/SiO₂/Si structures annealed at 600 °C and 800 °C, the XRD spectra of as-deposited and annealed at 400 °C sample pointed out Gd silicate formation. –Si, –O, –Gd, and –H bonds were defined in the FTIR spectra of all samples. The frequency dependent capacitance–voltage (C–V) and conductance–voltage (G/ω–V) characteristics of Gd₂O₃/SiO₂ MOS capacitor were measured. Strong accumulation capacitance values in these devices did not change significantly depending on frequency. Unlike from the MOS capacitor with as-deposited and annealed Gd₂O₃/SiO₂ at 400 °C, the interface trap charge density \(({N_{it}})\) increased with increasing voltage frequency for the samples annealed at 600 °C and 800 °C. No significant change in the border trap density \(({N_{bt}})\) with increasing frequency was observed in the MOS capacitor except for as-deposited device. The barrier height \(({\Phi _B})\) increased with increasing frequency for all Gd₂O₃/SiO₂ MOS capacitors.