2014 | OriginalPaper | Buchkapitel
Improved Performance of Junctionless Tunnel FETs with Source/Channel Heterostructure
verfasst von : Suresh Gundapaneni, Aniruddha Konar, Mohit Bajaj, K. V. R. M. Murali
Erschienen in: Physics of Semiconductor Devices
Verlag: Springer International Publishing
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We propose a junctionless tunnel FET architecture with a heterostructure at the source/channel interface. We show that the use of a low bandgap material in the source of this device results in significant ON current improvement. We further show that ON current improvement can also be achieved by using a low-k isolation dielectric. The proposed device architecture which combines the merits of both junctionless FETs and Tunnel FETs can be a potential candidate for sub-20 nm technology node.