1 Introduction
2 HiLiTE Test Generation Approach
product
block is the BUT, the test case template (Fig. 2) assigns the two inputs with non-zero values 2 and 4 respectively. After the backward and forward propagation search, the generated test vectors are given in Fig. 2 where blue column heading denotes model input and green denotes model output.
switch
block is the BUT, the equivalence class requires different values at its data inputs (FalseIn
, TrueIn
) to verify unique impact of an input on the block’s output. One test case template assigns 44 to FalseIn
and 46 to TrueIn
, but this leads to a conflict at the model input AdjustPct
after backward computation through the two look-up tables since their data points are in the same range. HiLiTE then further tries several alternative templates based on heuristics, yet all result in search failure. The root cause is that HiLiTE templates heuristics in the equivalence class domain prematurely pick block’s local input values, while this problem involves taking into account constraints imposed by the look-up table blocks driven by the same input AdjustPct
.3 Applying SMT Solving in Test Case Generation
3.1 Formal Specification of Equivalence Classes of Block Behaviors
switch
block with rule names in blue. Each rule is automatically translated, based upon formal definitions, into SMT logic formula in a straightforward way. For example, “Exists” for port TrueIn
is evaluated to “true
” if any value is present, “NEQ(FalseIn
, TrueIn
)” of port FalseIn
is interpreted as “FalseIn
\(\ne \) TrueIn
”, and “Equal(Control
, 1
)” of port Control
is interpreted as “Control
= true
” since Control
has a Boolean type. The overall SMT logic formula for an equivalence class is the conjunction of individual formulas translated from equivalence class rules for each block port. E.g., the equivalence class “Verify TRUE Input” corresponds to “(FalseIn
\(\ne \) TrueIn
)\(\wedge \)(Control
= true
)”.3.2 SMT Logic Formula for the Blocks’ Computation
-
Sum: \(\bigwedge _{j=0}^{m-1}(\texttt {Out}_j=\Sigma _{i=1}^{n}{} \texttt {In\_i}_j)\).
-
Comparator: \(\bigwedge _{j=0}^{m-1}(\texttt {Out}_j=\texttt {In\_1}_j \sim \texttt {In\_2}_j)\), \(\sim \in \{=,\ne ,>,<,\ge ,\le \}\).
-
Switch: \(\bigwedge _{j=0}^{m-1}(((!\texttt {In\_3}_j)\wedge (\texttt {Out}_j=\texttt {In\_1}_j))\vee (\texttt {In\_3}_j\wedge (\texttt {Out}_j=\texttt {In\_2}_j)))\).
-
1D Look-up Table: \(\bigwedge _{j=0}^{m-1}((\bigvee _{i=1}^n ((\texttt {In}_j\in Range_i)\wedge (\texttt {Out}_j=f_i(\texttt {In}_j))))\), where \(f_i\) is a linear function of \(\texttt {In}_j\) given the value of \(\texttt {In}_j\) in \(Range_i\).
-
UnitDelay: \((\texttt {Out}_0={initial\_constant})\wedge \bigwedge _{j=1}^{m-1}(\texttt {Out}_j=\texttt {In}_{j-1})\).
UnitDelay
) also allows us to explore feedback loops in the model for bounded number of steps.3.3 Formulated SMT Problem
sin
) not supported by SMT solving, HiLiTE identifies those blocks, records them as pending, and explores the neighbor paths, resulting in an incomplete subgraph. The pending blocks and their upstream blocks are excluded from the solution returned by SMT solver. HiLiTE normal method then picks up from here to further propagate the pending values. An improvement can be done if the backward search goes through a switch block, only one data input of which has pending block(s) on its upstream. The values on the branch with pending block(s) do not matter if we force the switch block to disable that branch. This is done by modifying the SMT logic formula of that switch block. Suppose port In_1
of block switch
is to be disabled, then the SMT logic formula becomes \(\bigwedge _{j=0}^{m-1}(\texttt {In\_3}_j\wedge (\texttt {Out}_j=\texttt {In\_2}_j))\).
3.4 Tool Architecture
switch
block output through the forward path to the model output GainAdj
via the intervening product
block, using a non-zero value for the second input of product
block to ensure observability. This process results in valid test cases (Fig. 5) for the switch
block in Fig. 2.