Internally Compensated LDO Regulators for Modern System-on-Chip Design

The continuous downscaling of semiconductor technology, predicted by Gordon Moore in 1965, has had a major impact on the development of integrated electronics. The reduction of transistor size has allowed the integration of more and more devices in the same die, increasing the integration density. In addition, it has led to the reduction of fabrication costs, making the final product cheaper and more accessible. However, this increase in the functionality of an integrated circuit entails greater complexity in the generation and distribution of the different supply voltages required in a chip. As more systems are integrated into the same die, more biasing domains coexist requiring different noise, regulation and/or stability specifications to be simultaneously satisfied. Therefore, power management circuits have been acquiring greater significance as technology downscales, reaching a maximum at present, in the nanoscale era. Voltage regulators are key components for power management, as they provide a regulated, stable and noise-free supply voltage to the active blocks of an SoC. This chapter reviews the basics of voltage regulation with emphasis on linear regulators.

This chapter contains an introduction to Internally Compensated Low-Dropout (IC-LDO) regulators. The design of these circuits and the most used Figures of Merit (FOMs) to evaluate their performances are studied. Special attention is paid to three aspects of their design: (a) stability. In IC-LDO regulators, the dominant pole is located at an inner node, while the non-dominant pole, located at the output, is responsible for the degradation of the stability. Furthermore, it depends on the load condition, which complicates the design of a compensation network. (b) Transient response: The regulator load usually requires fast transient response to load current and input voltage variations, and (c) power supply ripple rejection. Perturbations in the input voltage cause undesired disturbances in the output voltage. This chapter discusses the techniques proposed in the literature to face these design challenges, with emphasis on low power solutions. In addition, and based on a set of selected figures of merit, a comparison of recently published LDO regulators is made at the end of the chapter.

IC-LDO regulators are circuits that play a key role in modern power management and SoC design. They are required to occupy small area, operate with low power consumption and low supply voltage, and perform fast transient response and good load and line regulations. In addition, they must remain stable under extreme variations of the input voltage, load current and load capacitance. In this chapter, an adaptive and continuous compensation technique is proposed that tunes the value of the zero-nulling resistor of a classical Miller-based compensation to keep the nulling zero close to the Unit Gain Frequency (UGF), according to the working conditions. This technique has been applied to an LDO regulator based on a classical topology. Results of an implementation of such a regulator fabricated in a standard 65 nm CMOS technology are shown at the end of the chapter.

This chapter discusses challenges introduced by ultra-low power consumption in power management circuits. First of all, some techniques proposed in the literature to design ultra-low-power LDO regulators are reviewed. Then, an IC-LDO regulator with a quiescent current consumption lower than 600 nA is proposed. It is based on the classical LDO topology, which has been modified to include a class AB buffer between the output of the error amplifier and the gate of M\(_\mathrm{PASS}\). This way, a fast charge/discharge of its parasitic capacitance is achieved with the inherent low quiescent power consumption of class AB circuits. The proposed regulator has been fabricated in a standard 0.18 \(\upmu \)m CMOS technology. Experimental results show that the proposed regulator has a Figure of Merit in the state of the art.

To overcome the limitations of the classical topology to build IC-LDO regulators, several authors have chosen alternative topologies. This is the case of the Flipped Voltage Follower cell (proposed by Ramirez-Angulo et al., ISCAS 2002), which meets the requirements of LDO regulators as a consequence of its low output impedance and good stability. The first use of this cell as part of a linear regulator due to Pulkin and Rincon-Mora (U.S. Patent No. 6,573,694, 2003), where the Cascode Flipped Voltage Follower cell was used as a buffer to drive the pass transistor. Later, this same cell was used in an LDO regulator as a power stage (Hazucha et al., JSSC 40(4), 2005). This chapter describes the FVF and CAFVF cells and their performances as an LDO regulator, highlighting their advantages and disadvantages when compared to the classical topology. Then, it offers a thorough review of the regulators presented in the literature that use the FVF family of cells. Finally, a new regulator is presented that improves the performances of CAFVF-based regulators both in regulation and transient response.

As a consequence of technology downscaling, the coexistence of complex subsystems in the same chip becomes plausible, leading to the SoC paradigm. However, this technological evolution entails an increase in the complexity of power management systems, as different voltage supply domains, with different requirements of voltage level, ripple, maximum capacitive load and maximum output current, coexist in the same chip.