Weitere Kapitel dieses Buchs durch Wischen aufrufen
This chapter contains an introduction to Internally Compensated Low-Dropout (IC-LDO) regulators. The design of these circuits and the most used Figures of Merit (FOMs) to evaluate their performances are studied. Special attention is paid to three aspects of their design: (a) stability. In IC-LDO regulators, the dominant pole is located at an inner node, while the non-dominant pole, located at the output, is responsible for the degradation of the stability. Furthermore, it depends on the load condition, which complicates the design of a compensation network. (b) Transient response: The regulator load usually requires fast transient response to load current and input voltage variations, and (c) power supply ripple rejection. Perturbations in the input voltage cause undesired disturbances in the output voltage. This chapter discusses the techniques proposed in the literature to face these design challenges, with emphasis on low power solutions. In addition, and based on a set of selected figures of merit, a comparison of recently published LDO regulators is made at the end of the chapter.
Bitte loggen Sie sich ein, um Zugang zu diesem Inhalt zu erhalten
Sie möchten Zugang zu diesem Inhalt erhalten? Dann informieren Sie sich jetzt über unsere Produkte:
DVS is a method of reducing the average power consumption in embedded systems. This is accomplished by reducing the switching losses of the system by selectively reducing the frequency and voltage of the system.
Note that this definition is misleading. Despite the PSRR is defined in Eq. 2.14 to be a rejection ratio, it increases when the rejection to power supply perturbations diminishes. However, this definition is maintained here due to its wide use in LDO regulators’ literature.
- Internally Compensated LDO Regulators
José María Hinojo
Clara Luján Martínez
- Chapter 2