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2017 | OriginalPaper | Buchkapitel

1. Introduction

verfasst von : Felix Winterstein

Erschienen in: Separation Logic for High-level Synthesis

Verlag: Springer International Publishing

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Abstract

With the increasing demand for performance and efficiency of computing devices, custom computing is a growing area in digital computation today, which represents a class of processing devices that are dedicated to an application. This chapter introduces custom computing using FPGAs and high-level synthesis. It discusses the challenges in state-of-the-art high-level synthesis flows and introduces the research contributions made in this thesis.

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Literatur
1.
Zurück zum Zitat J. Fowers, G. Brown, P. Cooke, G. Stitt, A performance and energy comparison of fpgas, gpus, and multicores for sliding-window applications,” in Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA) (2012), pp. 47–56 J. Fowers, G. Brown, P. Cooke, G. Stitt, A performance and energy comparison of fpgas, gpus, and multicores for sliding-window applications,” in Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA) (2012), pp. 47–56
2.
Zurück zum Zitat B. Cope, P.Y.K. Cheung, W. Luk, L. Howes, Performance comparison of graphics processors to reconfigurable logic: a case study. IEEE Trans. Comput. 59(4), 433–448 (2010)MathSciNetCrossRef B. Cope, P.Y.K. Cheung, W. Luk, L. Howes, Performance comparison of graphics processors to reconfigurable logic: a case study. IEEE Trans. Comput. 59(4), 433–448 (2010)MathSciNetCrossRef
3.
Zurück zum Zitat A. Putnam, A. Caulfield, E. Chung, D. Chiou, K. Constantinides, J. Demme, H. Esmaeilzadeh, J. Fowers, G. Gopal, J. Gray, M. Haselman, S. Hauck, S. Heil, A. Hormati, J.-Y. Kim, S. Lanka, J. Larus, E. Peterson, S. Pope, A. Smith, J. Thong, P. Xiao, D. Burger, A reconfigurable fabric for accelerating large-scale datacenter services, in Proceedings of the ACM/IEEE International Symposium on Computer Architecture (ISCA) (2014), pp. 13–24 A. Putnam, A. Caulfield, E. Chung, D. Chiou, K. Constantinides, J. Demme, H. Esmaeilzadeh, J. Fowers, G. Gopal, J. Gray, M. Haselman, S. Hauck, S. Heil, A. Hormati, J.-Y. Kim, S. Lanka, J. Larus, E. Peterson, S. Pope, A. Smith, J. Thong, P. Xiao, D. Burger, A reconfigurable fabric for accelerating large-scale datacenter services, in Proceedings of the ACM/IEEE International Symposium on Computer Architecture (ISCA) (2014), pp. 13–24
4.
Zurück zum Zitat Z.K. Baker, M.B. Gokhale, J.L. Tripp, Matched Filter Computation on FPGA, Cell and GPU, in Proceedings of the IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) (2007), pp. 207–218 Z.K. Baker, M.B. Gokhale, J.L. Tripp, Matched Filter Computation on FPGA, Cell and GPU, in Proceedings of the IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) (2007), pp. 207–218
5.
Zurück zum Zitat H. Riebler, T. Kenter, C. Plessl, C. Sorge, Reconstructing AES key schedules from decayed memory with FPGAs, in Proceedings of the IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) (2014), pp. 222–229 H. Riebler, T. Kenter, C. Plessl, C. Sorge, Reconstructing AES key schedules from decayed memory with FPGAs, in Proceedings of the IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) (2014), pp. 222–229
6.
Zurück zum Zitat J. Chase, B. Nelson, J. Bodily, Z. Wei, D.J. Lee, Real-time optical flow calculations on FPGA and GPU architectures: a comparison study, in Proceedings of the IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) (2008), pp. 173–182 J. Chase, B. Nelson, J. Bodily, Z. Wei, D.J. Lee, Real-time optical flow calculations on FPGA and GPU architectures: a comparison study, in Proceedings of the IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) (2008), pp. 173–182
7.
Zurück zum Zitat S. Asano, T. Maruyama, Y. Yamaguchi, Performance comparison of FPGA, GPU and CPU in image processing, in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) (2009), pp. 126–131 S. Asano, T. Maruyama, Y. Yamaguchi, Performance comparison of FPGA, GPU and CPU in image processing, in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) (2009), pp. 126–131
8.
Zurück zum Zitat H. Park, S. Vijayvargiya, A. DeHon, Energy minimization in the time-space continuum, in Proceedings of the International Conference on Field Programmable Technology (ICFPT) (2015), pp. 64–71 H. Park, S. Vijayvargiya, A. DeHon, Energy minimization in the time-space continuum, in Proceedings of the International Conference on Field Programmable Technology (ICFPT) (2015), pp. 64–71
9.
Zurück zum Zitat J. Qiu, J. Wang, S. Yao, K. Guo, B. Li, E. Zhou, J. Yu, T. Tang, N. Xu, S. Song, Y. Wang, H. Yang, Going deeper with embedded FPGA platform for convolutional neural network, in Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (2016), pp. 26–35 J. Qiu, J. Wang, S. Yao, K. Guo, B. Li, E. Zhou, J. Yu, T. Tang, N. Xu, S. Song, Y. Wang, H. Yang, Going deeper with embedded FPGA platform for convolutional neural network, in Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (2016), pp. 26–35
10.
Zurück zum Zitat IEEE Standard VHDL Language Reference Manual, IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002) (2009), pp. 1–626 IEEE Standard VHDL Language Reference Manual, IEEE Std 1076-2008 (Revision of IEEE Std 1076-2002) (2009), pp. 1–626
11.
Zurück zum Zitat IEEE Standard for Verilog Hardware Description Language, IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001) (2006), pp. 1–560 IEEE Standard for Verilog Hardware Description Language, IEEE Std 1364-2005 (Revision of IEEE Std 1364-2001) (2006), pp. 1–560
12.
Zurück zum Zitat D. Bacon, R. Rabbah, S. Shukla, FPGA programming for the masses. Queue 11(2), 40:40–40:52 (2013) D. Bacon, R. Rabbah, S. Shukla, FPGA programming for the masses. Queue 11(2), 40:40–40:52 (2013)
24.
Zurück zum Zitat C. Pilato, F. Ferrandi, Bambu: a modular framework for the high level synthesis of memory-intensive applications, in Proceedings International Conference on Field Programmable Logic and Applications (FPL) (2013), pp. 1–4 C. Pilato, F. Ferrandi, Bambu: a modular framework for the high level synthesis of memory-intensive applications, in Proceedings International Conference on Field Programmable Logic and Applications (FPL) (2013), pp. 1–4
26.
Zurück zum Zitat R. Nane, V. M. Sima, B. Olivier, R. Meeuws, Y. Yankova, K. Bertels, DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler, in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) (2012), pp. 619–622 R. Nane, V. M. Sima, B. Olivier, R. Meeuws, Y. Yankova, K. Bertels, DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler, in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) (2012), pp. 619–622
28.
Zurück zum Zitat G. Martin, G. Smith, High-level synthesis: past, present, and future. IEEE Des. Test Comput. 26(4), 18–25 (2009)CrossRef G. Martin, G. Smith, High-level synthesis: past, present, and future. IEEE Des. Test Comput. 26(4), 18–25 (2009)CrossRef
29.
Zurück zum Zitat W. Meeus, K. Van Beeck, T. Goedemé, J. Meel, D. Stroobandt, An overview of todays high-level synthesis tools. Des. Autom. Emb. Syst., pp. 1–21 (2012) W. Meeus, K. Van Beeck, T. Goedemé, J. Meel, D. Stroobandt, An overview of todays high-level synthesis tools. Des. Autom. Emb. Syst., pp. 1–21 (2012)
31.
Zurück zum Zitat F. Winterstein, S. Bayliss, G. Constantinides, High-level synthesis of dynamic data structures: a case study using Vivado HLS, in Proceedings of the International Conference on Field-Programmable Technology (ICFPT) (2013), pp. 362–365 F. Winterstein, S. Bayliss, G. Constantinides, High-level synthesis of dynamic data structures: a case study using Vivado HLS, in Proceedings of the International Conference on Field-Programmable Technology (ICFPT) (2013), pp. 362–365
32.
Zurück zum Zitat R. Nane, V.-M. Sima, C. Pilato, J. Choi, B. Fort, A. Canis, Y.T. Chen, H. Hsiao, S. Brown, F. Ferrandi, J. Anderson, K. Bertels, A survey and evaluation of FPGA high-level synthesis tools, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. http://janders.eecg.toronto.edu/pdfs/tcad_hls.pdf. Accessed 28 Feb 2016 R. Nane, V.-M. Sima, C. Pilato, J. Choi, B. Fort, A. Canis, Y.T. Chen, H. Hsiao, S. Brown, F. Ferrandi, J. Anderson, K. Bertels, A survey and evaluation of FPGA high-level synthesis tools, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. http://​janders.​eecg.​toronto.​edu/​pdfs/​tcad_​hls.​pdf. Accessed 28 Feb 2016
33.
Zurück zum Zitat S. Sarkar, S. Dabral, P. Tiwari, R. Mitra, Lessons and experiences with high-level synthesis. IEEE Des. Test Comput. 26(4), 34–45 (2009) S. Sarkar, S. Dabral, P. Tiwari, R. Mitra, Lessons and experiences with high-level synthesis. IEEE Des. Test Comput. 26(4), 34–45 (2009)
34.
Zurück zum Zitat P. O’Hearn, J. Reynolds, H. Yang, Local reasoning about programs that alter data structures, in Computer Science Logic, ed. by L. Fribourg, Lecture Notes Series, in Computer Science, vol. 2142, (Springer, Heidelberg, 2001), pp. 1–19 P. O’Hearn, J. Reynolds, H. Yang, Local reasoning about programs that alter data structures, in Computer Science Logic, ed. by L. Fribourg, Lecture Notes Series, in Computer Science, vol. 2142, (Springer, Heidelberg, 2001), pp. 1–19
35.
Zurück zum Zitat F.J. Winterstein, S.R. Bayliss, G.A. Constantinides, Separation logic for high-level synthesis. ACM Trans. Reconfigurable Technol. Syst. 9(2), 10:1–10:23 (2015) F.J. Winterstein, S.R. Bayliss, G.A. Constantinides, Separation logic for high-level synthesis. ACM Trans. Reconfigurable Technol. Syst. 9(2), 10:1–10:23 (2015)
36.
Zurück zum Zitat F. Winterstein, K. Fleming, H.-J. Yang, J. Wickerson, G. Constantinides, Custom-sized caches in application-specific memory hierarchies, in Proceedings of the International Conference on Field Programmable Technology (ICFPT) (2015), pp. 144–151 F. Winterstein, K. Fleming, H.-J. Yang, J. Wickerson, G. Constantinides, Custom-sized caches in application-specific memory hierarchies, in Proceedings of the International Conference on Field Programmable Technology (ICFPT) (2015), pp. 144–151
37.
Zurück zum Zitat F. Winterstein, K. Fleming, H.-J. Yang, S. Bayliss, G. Constantinides, MATCHUP: memory abstractions for heap manipulating programs, in Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) (2015), pp. 136–145 F. Winterstein, K. Fleming, H.-J. Yang, S. Bayliss, G. Constantinides, MATCHUP: memory abstractions for heap manipulating programs, in Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) (2015), pp. 136–145
38.
Zurück zum Zitat F. Winterstein, S. Bayliss, G.A. Constantinides, Separation logic-assisted code transformations for efficient high-level synthesis, in Proceedings of the IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) (2014), pp. 1–8 F. Winterstein, S. Bayliss, G.A. Constantinides, Separation logic-assisted code transformations for efficient high-level synthesis, in Proceedings of the IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) (2014), pp. 1–8
39.
Zurück zum Zitat F. Winterstein, S. Bayliss, G. Constantinides, FPGA-based K-means clustering using tree-based data structures, in Proceedings International Conference on Field Programmable Logic and Applications (FPL) (2013), pp. 1–6 F. Winterstein, S. Bayliss, G. Constantinides, FPGA-based K-means clustering using tree-based data structures, in Proceedings International Conference on Field Programmable Logic and Applications (FPL) (2013), pp. 1–6
41.
Zurück zum Zitat K. Fleming, H.-J. Yang, M. Adler, J. Emer, The LEAP FPGA operating system,” in Proceedings of the International Symposium on Field Programmable Logic and Applications (FPL) (2014), pp. 1–8 K. Fleming, H.-J. Yang, M. Adler, J. Emer, The LEAP FPGA operating system,” in Proceedings of the International Symposium on Field Programmable Logic and Applications (FPL) (2014), pp. 1–8
42.
Zurück zum Zitat H.-J. Yang, K. Fleming, M. Adler, F. Winterstein, J. Emer, LMC: automatic resource-aware program-optimized memory partitioning, in Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) (2016), pp. 128–137 H.-J. Yang, K. Fleming, M. Adler, F. Winterstein, J. Emer, LMC: automatic resource-aware program-optimized memory partitioning, in Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) (2016), pp. 128–137
43.
Zurück zum Zitat H.-J. Yang, K. Fleming, M. Adler, F. Winterstein, J. Emer, Scavenger: automating the construction of application-optimized memory hierarchies, in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) (2015), pp. 1–8 H.-J. Yang, K. Fleming, M. Adler, F. Winterstein, J. Emer, Scavenger: automating the construction of application-optimized memory hierarchies, in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) (2015), pp. 1–8
46.
Zurück zum Zitat N. Ramanathan, J. Wickerson, F. Winterstein, G.A. Constantinides, A case for work-stealing on FPGAs with OpenCL atomics,” in Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) (2016), pp. 48–53 N. Ramanathan, J. Wickerson, F. Winterstein, G.A. Constantinides, A case for work-stealing on FPGAs with OpenCL atomics,” in Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) (2016), pp. 48–53
47.
Zurück zum Zitat S.T. Fleming, D.B. Thomas, F. Winterstein, FPGAs and Parallel Architectures for Aerospace Applications: Soft Errors and Fault-Tolerant Design, pp. 75–90 (Springer International Publishing, Heidelberg, 2016). (ch. A Power-Aware Adaptive FDIR Framework Using Heterogeneous System-on-Chip Modules) S.T. Fleming, D.B. Thomas, F. Winterstein, FPGAs and Parallel Architectures for Aerospace Applications: Soft Errors and Fault-Tolerant Design, pp. 75–90 (Springer International Publishing, Heidelberg, 2016). (ch. A Power-Aware Adaptive FDIR Framework Using Heterogeneous System-on-Chip Modules)
48.
Zurück zum Zitat E.A. Pelaez, S. Bayliss, A. Smith, F. Winterstein, D.R. Ghica, D. Thomas, G.A. Constantinides, Compiling higher order functional programs to composable digital hardware, in Proceedings of the IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) (2014), pp. 234–234 E.A. Pelaez, S. Bayliss, A. Smith, F. Winterstein, D.R. Ghica, D. Thomas, G.A. Constantinides, Compiling higher order functional programs to composable digital hardware, in Proceedings of the IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) (2014), pp. 234–234
Metadaten
Titel
Introduction
verfasst von
Felix Winterstein
Copyright-Jahr
2017
DOI
https://doi.org/10.1007/978-3-319-53222-6_1

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