Introduction

The subject of this book, design problems which require an integrated knowledge of logical and timing behavior, is perhaps best introduced by examining a typical process of designing high performance digital circuits. Suppose a logic design is synthesized from a specification manually, e.g. using Kamauph maps, or automatically, e.g. using SIS of UC Berkeley [1231. For example, the circuit in is an implementation of a 4-bit carry bypass adder, where (A₁...., A₄) and (B1,...., B₄) are the two input vectors to be added, Cinis the carry input, Si, i = 1,...., 4 are the sum bits and C_out is the carry output. It is called a carry bypass adder because when the input values are such that a carry input in a normal adder would ripple through the four adding stages, i.e. C₁, C₂, C₃, C₄, to the carry output, a carry input in this carry bypass adder will bypass the adding stages and propagate directly to the carry output through the multiplexer. The advantage is that this bypass feature speeds up the arrival time of the carry output.