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Erschienen in:
2010 | OriginalPaper | Buchkapitel
1. Introduction
verfasst von : Amith Singhee
Erschienen in: Extreme Statistics in Nanoscale Memory Design
Verlag: Springer US
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Abstract
Tradition VLSI circuit design would contend with three general objectives Maximize performance: In the context of an SRAM bitcell, this may be captured by several different metrics, for example, the read current supplied by the cell, or the read access time, given a specific peripheral circuit. Minimize power consumption: For an SRAM bitcell, this could be, for instance, the active current drawn by the cell during a read operation, or the total leakage current drawn by the cell during standby. Maximize noise and noise susceptibility: Several metrics may measure robustness of the circuit operation to noise. Again for an SRAM bitcell, a measure can be the static noise margin (SNM) of the cell.