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2020 | OriginalPaper | Buchkapitel

1. Introduction

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Abstract

There has been tremendous growth in the semiconductor industry in the last few decades. This has largely followed Gordon Moore’s prediction in the 1960s that number of transistors per chip would double every two years approximately. However, there have been concerns about scaling limits of silicon MOSFETs during the last twenty years [1]. As a consequence, variations of the basic theme have been suggested and two categories have emerged, one of which attempts further miniaturization while the other aims at diversification.

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Literatur
1.
Zurück zum Zitat Frank, D.J., Dennard, R.H., Nowak, E., Solomon, P.M., Tuar, Y., Wong, H.S.P.: Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE 89(3), 259–288 (2001) Frank, D.J., Dennard, R.H., Nowak, E., Solomon, P.M., Tuar, Y., Wong, H.S.P.: Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE 89(3), 259–288 (2001)
3.
Zurück zum Zitat Balestra, F., Cristoloveanu, S., Benachir, M., Elwa, T.: Double-gate silicon-on-insulator transistor with volume inversion : a new device with greatly enhanced performance. IEEE Electron Devices Lett. 8(9), 410–412 (1987) Balestra, F., Cristoloveanu, S., Benachir, M., Elwa, T.: Double-gate silicon-on-insulator transistor with volume inversion : a new device with greatly enhanced performance. IEEE Electron Devices Lett. 8(9), 410–412 (1987)
4.
Zurück zum Zitat Huang, X., Lee, W.-C., Ku, C., Hisamoto, D., Chang, L., Kedzierski, J., Anderson, E., Takeuchi, H., Choi, Y.-K., Asano, K., Subramanian, V., King, T.J., Bokor, J., Hu, C.: Sub 50-nm FinFET: PMOS. IEDM Tech. Digest, 67–70 (1999) Huang, X., Lee, W.-C., Ku, C., Hisamoto, D., Chang, L., Kedzierski, J., Anderson, E., Takeuchi, H., Choi, Y.-K., Asano, K., Subramanian, V., King, T.J., Bokor, J., Hu, C.: Sub 50-nm FinFET: PMOS. IEDM Tech. Digest, 67–70 (1999)
5.
Zurück zum Zitat Dresselhaus, M., Mavroides, J.G.: The Fermi structure of graphite. IBM J. Res. Develop. 8(3), 262–267 (1964) Dresselhaus, M., Mavroides, J.G.: The Fermi structure of graphite. IBM J. Res. Develop. 8(3), 262–267 (1964)
6.
Zurück zum Zitat Atkins, P., de Paula, J.: Physical Chemistry, 9th edn. W.H. Freeman (2009) Atkins, P., de Paula, J.: Physical Chemistry, 9th edn. W.H. Freeman (2009)
7.
Zurück zum Zitat Bachtold, A., Hadley, P., Nakanishi, T., Dekker, C.: Logic circuits with carbon-nanotube transistors. Science 294(5545), 1317–1320 (2001) Bachtold, A., Hadley, P., Nakanishi, T., Dekker, C.: Logic circuits with carbon-nanotube transistors. Science 294(5545), 1317–1320 (2001)
8.
Zurück zum Zitat Zhang, J., Patil, N., Mitra, S.: Probabilistic Analysis and design of metallic-carbon-nanotube-tolerant digital logic circuits. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 28(9), 1307–1320 (2009) Zhang, J., Patil, N., Mitra, S.: Probabilistic Analysis and design of metallic-carbon-nanotube-tolerant digital logic circuits. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 28(9), 1307–1320 (2009)
9.
Zurück zum Zitat Shulaker, M.M., Hills, G., Patil, N., Wei, H., Chen, H.-Y., Wong, H.-S.P., Mitra, S.: Carbon nanotube computer. Nature 501, 526–535 (2013) Shulaker, M.M., Hills, G., Patil, N., Wei, H., Chen, H.-Y., Wong, H.-S.P., Mitra, S.: Carbon nanotube computer. Nature 501, 526–535 (2013)
10.
Zurück zum Zitat Hills, G., Lau, C., Wright, A., Fuller, S., Bishop, M.D., Srimani, T., Kanhaiya, P., Ho, R., Amer, A., Stein, Y., Murphy, D., Arvind, Chandrakasan, A., Shulaker, M.M.: Modern microprocessor built from complementary carbon nanotube transistors. Nature 572, 595–602 (2019) Hills, G., Lau, C., Wright, A., Fuller, S., Bishop, M.D., Srimani, T., Kanhaiya, P., Ho, R., Amer, A., Stein, Y., Murphy, D., Arvind, Chandrakasan, A., Shulaker, M.M.: Modern microprocessor built from complementary carbon nanotube transistors. Nature 572, 595–602 (2019)
11.
Zurück zum Zitat Raychowdhury, A., Roy, K.: Carbon-Nanotube-based voltage-mode multiple-valued logic design. IEEE Trans. Nanotechnol. 4(2), 168–179 (2005) Raychowdhury, A., Roy, K.: Carbon-Nanotube-based voltage-mode multiple-valued logic design. IEEE Trans. Nanotechnol. 4(2), 168–179 (2005)
12.
Zurück zum Zitat Lin, S., Kim, Y.B., Lombardi, F.: CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. Nanotechnol. 10(2), 217–225 (2011) Lin, S., Kim, Y.B., Lombardi, F.: CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. Nanotechnol. 10(2), 217–225 (2011)
13.
Zurück zum Zitat Moaiyeri, M.H., Doostaregan, A., Navi, K.: Design of energy-efficient and robust ternary circuits for nanotechnology. IET Circuits, Devices, Syst. 5(4), 285–296 (2011) Moaiyeri, M.H., Doostaregan, A., Navi, K.: Design of energy-efficient and robust ternary circuits for nanotechnology. IET Circuits, Devices, Syst. 5(4), 285–296 (2011)
14.
Zurück zum Zitat Miller, D.M., Thornton, M.A.: Multiple Valued Logic: Concepts and Representations. Morgan and Claypool Publishers (2008) Miller, D.M., Thornton, M.A.: Multiple Valued Logic: Concepts and Representations. Morgan and Claypool Publishers (2008)
15.
Zurück zum Zitat Keshavarzian, P., Sarikhani, R.: A novel CNTFET-based ternary full adder. Circuits, Syst. Signal Process. 33, 665–679 (2014) Keshavarzian, P., Sarikhani, R.: A novel CNTFET-based ternary full adder. Circuits, Syst. Signal Process. 33, 665–679 (2014)
16.
Zurück zum Zitat Hurst, S.L.: An extension of binary minimization techniques to ternary equations. Comput. J. 11(3), 277–286 (1968) Hurst, S.L.: An extension of binary minimization techniques to ternary equations. Comput. J. 11(3), 277–286 (1968)
17.
Zurück zum Zitat Halpern, I., Yoeli, M.: Ternary arithmetic unit. Proc. IEE 115(10), 1385–1388 (1968) Halpern, I., Yoeli, M.: Ternary arithmetic unit. Proc. IEE 115(10), 1385–1388 (1968)
18.
Zurück zum Zitat Kameyama, M., Kawahito, S., Higuchi, T.: A Multiplier Chip with multiple-valued bidirectional current-mode logic circuits. IEEE Comput. 23(4), 43–56 (1988) Kameyama, M., Kawahito, S., Higuchi, T.: A Multiplier Chip with multiple-valued bidirectional current-mode logic circuits. IEEE Comput. 23(4), 43–56 (1988)
19.
Zurück zum Zitat Mouftah, H.T., Jordan, I.B.: Design of ternary COS/MOS memory and sequential circuits. IEEE Trans. Comput. 281–288 (1977) Mouftah, H.T., Jordan, I.B.: Design of ternary COS/MOS memory and sequential circuits. IEEE Trans. Comput. 281–288 (1977)
20.
Zurück zum Zitat Mouftah, H.T., Smith, K.C.: Design and implementation of three-valued logic systems with MOS integrated circuits. IEE Proc. Part G 127(4), 165–168 (1980) Mouftah, H.T., Smith, K.C.: Design and implementation of three-valued logic systems with MOS integrated circuits. IEE Proc. Part G 127(4), 165–168 (1980)
21.
Zurück zum Zitat Wu, X.W., Prosser, F.P.: CMOS ternary logic circuits. IEEE Proc. Circuits, Devices Syst. 137(1), 21–27 (1990) Wu, X.W., Prosser, F.P.: CMOS ternary logic circuits. IEEE Proc. Circuits, Devices Syst. 137(1), 21–27 (1990)
22.
Zurück zum Zitat Srivastava, A., Venkatapathy, K.: Design and implementation of a low power ternary full adder. VLSI Design 4(1), 75–81 (1996) Srivastava, A., Venkatapathy, K.: Design and implementation of a low power ternary full adder. VLSI Design 4(1), 75–81 (1996)
23.
Zurück zum Zitat Mateo, D., Rubio, A.: Design and implementation of a 5 \(\times \) 5 trits multiplier in a quasi-adiabatic ternary CMOS logic. IEEE J. Solid-State Circuits 33(7), 1111–1116 (1998) Mateo, D., Rubio, A.: Design and implementation of a 5 \(\times \) 5 trits multiplier in a quasi-adiabatic ternary CMOS logic. IEEE J. Solid-State Circuits 33(7), 1111–1116 (1998)
24.
Zurück zum Zitat Navi, K., Rashtian, M., Khatir, A., Keshavarzian, P.: High speed capacitor-inverter based carbon nanotube full adder. Nanoscale Res. Lett. 5, 859–862 (2010) Navi, K., Rashtian, M., Khatir, A., Keshavarzian, P.: High speed capacitor-inverter based carbon nanotube full adder. Nanoscale Res. Lett. 5, 859–862 (2010)
25.
Zurück zum Zitat Lin, A., Patil, N., Wei, H., Mitra, S., Wong, H.S.P.: ACCNT—a Metallic-CNT-tolerant design methodology for carbon-nanotube VLSI : concepts and experimental demonstration. IEEE Trans. Electron Devices 56(12), 2969–2978 (2009) Lin, A., Patil, N., Wei, H., Mitra, S., Wong, H.S.P.: ACCNT—a Metallic-CNT-tolerant design methodology for carbon-nanotube VLSI : concepts and experimental demonstration. IEEE Trans. Electron Devices 56(12), 2969–2978 (2009)
26.
Zurück zum Zitat Sharma, T., Kumre, L.: CNTFET based design of ternary arithmetic modules. Circuits, Syst. Signal Process. 38, 4640–4666 (2019) Sharma, T., Kumre, L.: CNTFET based design of ternary arithmetic modules. Circuits, Syst. Signal Process. 38, 4640–4666 (2019)
27.
Zurück zum Zitat Sahoo, S.K., Dhoot, K., Sahoo, R.: High performance ternary multiplier using CNTFET. In: Proceedings of 2018 IEEE Computer Society Annual Symposium on VLSI, pp. 269–274 (2018) Sahoo, S.K., Dhoot, K., Sahoo, R.: High performance ternary multiplier using CNTFET. In: Proceedings of 2018 IEEE Computer Society Annual Symposium on VLSI, pp. 269–274 (2018)
28.
Zurück zum Zitat E. Shahrom and S.A. Hosseini. A new low power multiplexer based ternary multiplier using CNTFETs. Int. J. Electron. Commun. (AEÜ) E. Shahrom and S.A. Hosseini. A new low power multiplexer based ternary multiplier using CNTFETs. Int. J. Electron. Commun. (AEÜ)
29.
Zurück zum Zitat Sharma, T., Kumre, L.: Design of low power multi-ternary digit multiplier in CNTFET technology. Microprocess. Microsyst. 73, 1–8 (2020) Sharma, T., Kumre, L.: Design of low power multi-ternary digit multiplier in CNTFET technology. Microprocess. Microsyst. 73, 1–8 (2020)
30.
Zurück zum Zitat Jaber, R.A., Kassem, A., El-Hajj, A.M., El-Nimri, L.A., Haidar, A.M.: High-performance and energy-efficient CNFET-based designs for ternary logic circuits. IEEE Access 7, 93871–93886 (2019) Jaber, R.A., Kassem, A., El-Hajj, A.M., El-Nimri, L.A., Haidar, A.M.: High-performance and energy-efficient CNFET-based designs for ternary logic circuits. IEEE Access 7, 93871–93886 (2019)
31.
Zurück zum Zitat Zarandi, A.D., Reshadinezhad, M.R., Rubio, A.: A systematic method to design efficient ternary high performance CNTFET-based logic cells. IEEE Access 8, 58585–58593 (2020) Zarandi, A.D., Reshadinezhad, M.R., Rubio, A.: A systematic method to design efficient ternary high performance CNTFET-based logic cells. IEEE Access 8, 58585–58593 (2020)
Metadaten
Titel
Introduction
verfasst von
K. Sridharan
B. Srinivasu
Vikramkumar Pudi
Copyright-Jahr
2020
DOI
https://doi.org/10.1007/978-3-030-50699-5_1

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