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2014 | OriginalPaper | Buchkapitel

1. Introduction

verfasst von : Haris Javaid, Sri Parameswaran

Erschienen in: Pipelined Multiprocessor System-on-Chip for Multimedia

Verlag: Springer International Publishing

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Abstract

This chapter of the monograph entails an overview of trends and challenges in multimedia applications and embedded architectures, starting from low resolution video processing on uniprocessor systems to high definition video processing on (heterogeneous) multiprocessor systems.

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Fußnoten
1
Measured in mW/Million Operations Per Second.
 
2
Measured in Million Operations Per Second/\(\text {mm}^{2}\).
 
3
Note that partitioning and mapping of a multimedia application on a pipelined MPSoC is done either manually or semi-automatically [99‐103].
 
Literatur
1.
M. Weiser, The computer for the 21st century. SIGMOBILE Mob. Comput. Commun. Rev. 3, 3–11 (1999)CrossRef
2.
M. Morales, S. Rau, M.J. Palma, M. Venkatesan, F. Pulskamp, A. Dugar, Worldwide intelligent systems 2011–2015 forecast: the next big opportunity. Technical report, International Data Corporation, September 2011
3.
C. Kozyrakis and D. Patterson, Vector vs. superscalar and vliw architectures for embedded multimedia benchmarks, in MICRO 35: Proceedings of the 35th Annual ACM/IEEE International Symposium on Microarchitecture, Los Alamitos, CA, USA, pp. 283–293 (IEEE Computer Society Press, 2002)
4.
K. Karuri, R. Leupers, Application analysis tools for ASIP design: application profiling and instruction-set customization (Springer, New York, 2011)CrossRef
5.
K. Keutzer, S. Malik, A. Newton, From asic to asip: the next design discontinuity, in Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 84–90 (2002)
6.
M. Shafique, Architectures for adaptive low-power embedded multimedia systems. Ph.D. thesis, Karlsruhe Institute of Technology, Germany (2011)
7.
J. Meehan, S. Busch, J. Noel, F. Noraz, Multimedia ip architecture trends in the mobile multimedia consumer device. Image Commun. 25, 317–324 (2010)
8.
K. Willner, K. Ugur, M. Salmimaa, A. Hallapuro, J. Lainema, Mobile 3D video using mvc and n800 internet tablet, in 3DTV Conference: The True Vision—Capture, Transmission and Display of 3D Video, 2008, pp. 69–72, May 2008
9.
10.
International Telecommunucation Union, Advanced video coding for generic audiovisual services, in Recommendation H.264 and ISO/IEC 14496–10:2005 (2005)
11.
Joint Video Team of ISO/IEC MPEG and I.-T. VCEG, Jvt-ab204: Joint draft 8.0 on multiview video coding (2008)
12.
T. Wiegand, G. Sullivan, G. Bjontegaard, A. Luthra, Overview of the h.264/avc video coding standard. IEEE Trans. Circ. Syst. Video Technol. 13, 560–576 (2003)CrossRef
13.
J. Ostermann, J. Bormans, P. List, D. Marpe, M. Narroschke, F. Pereira, T. Stockhammer, T. Wedi, Video coding with h.264/avc: tools, performance, and complexity. IEEE Circ. Syst. Mag. 4, 7–28 (2004)CrossRef
14.
C. Van Berkel, Multi-core for mobile phones, in Proceedings of the Design, Automation Test in Europe Conference Exhibition, 2009 (DATE ’09), pp. 1260–1265, April 2009
15.
16.
17.
18.
T. von Sydow, B. Neumann, H. Blume, T. G. Noll, Quantitative analysis of embedded fpga-architectures for arithmetic, in Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, 2006 (ASAP ’06), pp. 125–131, September 2006
19.
Y.-S. Huang, B.-C. Chieu, Architecture for video coding on a processor with an arm and dsp cores. Multimedia Tools Appl. 54, 527–543 (2011)CrossRef
20.
21.
D. Talla, L. John, V. Lapinskii, B. Evans, Evaluating signal processing and multimedia applications on simd, vliw and superscalar architectures, in Proceedings of the 2000 International Conference on Computer Design, pp. 163–172 (2000)
22.
23.
24.
25.
26.
27.
U.J. Kapasi, S. Rixner, W.J. Dally, B. Khailany, J.H. Ahn, P. Mattson, J.D. Owens, Programmable stream processors. Computer 36, 54–62 (2003)CrossRef
28.
G.G. Lee, Y.-K. Chen, M. Mattavelli, E.S. Jang, Algorithm/architecture co-exploration of visual computing on emergent platforms: overview and future prospects. IEEE Trans. Circ. Sys. Video Technol. 19, 1576–1587 (2009)CrossRef
29.
G. R. Stewart, Implementing video compression algorithms on reconfigurable devices. Ph.D. thesis, University of Glassgow (2009)
30.
S. Hu, Z. Zhang, M. Zhang, T. Sheng, Optimization of memory allocation for h.264 video decoder on digital signal processors, in Proceedings of the Congress on Image and Signal Processing, 2008 (CISP ’08), vol. 2, pp. 71–75, May 2008
31.
P. Ienne, R. Leupers, Customizable Embedded Processors: Design Technologies and Applications (Systems on Silicon) (Morgan Kaufmann Publishers, San Mateo, 2006)
32.
C. Valderrama, L. Jojczyk, P. Possa, J. Gazzano, Fpga and asic convergence, in Proceedings of the 2011 7th Southern Conference on Programmable Logic (SPL), pp. 269–274, April 2011
33.
34.
S. Damaraju, V. George, S. Jahagirdar, T. Khondker, R. Milstrey, S. Sarkar, S. Siers, I. Stolero, A. Subbiah, A 22nm ia multi-cpu and gpu system-on-chip, in Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 56–57, February 2012
35.
J. Henkel, S. Parameswaran, Designing Embedded Processors: A Low Power Perspective (Springer, New York, 2007)CrossRef
36.
S. Saponara, L. Fanucci, S. Marsi, G. Ramponi, D. Kammler, E. Witte, Application-specific instruction-set processor for retinex-like image and video processing. IEEE Trans. Circ. Syst. II: Express Briefs 54, 596–600 (2007)CrossRef
37.
S.D. Kim, M.H. Sunwoo, Asip approach for implementation of h.264/avc. J. Signal Process. Syst. 50(1), 53–67 (2008)CrossRef
38.
J. Janhunen, O. Silven, M. Juntti, M. Myllyla, Software defined radio implementation of k-best list sphere detector algorithm, in Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2008), pp. 100–107, July 2008
39.
A. Portero, G. Talavera, M. Moreno, J. Carrabina, F. Catthoor, Methodology for energy-flexibility space exploration and mapping of multimedia applications to single-processor platform styles. IEEE Trans. Circ. Syst. Video Technol. 21, 1027–1039 (2011)CrossRef
40.
41.
42.
43.
44.
45.
46.
47.
48.
S. Vassiliadis, S. Wong, G. Gaydadjiev, K. Bertels, G. Kuzmanov, E. Panainte, The molen polymorphic processor. IEEE Trans. Comput. 53, 1363–1375 (2004)CrossRef
49.
R. Lysecky, G. Stitt, F. Vahid, Warp processors. ACM Trans. Des. Autom. Electron. Syst. 11, 659–681 (2006)CrossRef
50.
L. Bauer, M. Shafique, J. Henkel, Rispp: a run-time adaptive reconfigurable embedded processor, in proceedings of the International Conference on Field Programmable Logic and Applications, 2009 (FPL 2009), pp. 725–726, 31 August–2 September 2009
51.
52.
53.
54.
H. Amano, A survey on dynamically reconfigurable processors, in Proceedings of the IEICE Transactions (2006)
55.
H.P. Huynh, T. Mitra, Runtime adaptive extensible embedded processors: a survey, in Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS ’09), pp. 215–225 (Springer, Berlin, 2009)
56.
57.
S.L. Shee, A. Erdos, S. Parameswaran, Heterogeneous multiprocessor implementations for jpeg: a case study, in CODES+ISSS ’06: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, pp. 217–222 (ACM, New York, 2006)
58.
S.L. Shee, A. Erdos, S. Parameswaran, Architectural exploration of heterogeneous multiprocessor systems for jpeg. Int. J. Parallel Prog. 36(1), 140–162 (2008)CrossRefMATH
59.
H.C. Doan, H. Javaid, S. Parameswaran, Multi-asip based parallel and scalable implementation of motion estimation kernel for high definition videos, in Proceedings of the 2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia), pp. 56–65, October 2011
60.
F. J. Pollack, New microarchitecture challenges in the coming generations of cmos process technologies (keynote address) (abstract only), in Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture (MICRO 32), p. 2 (IEEE Computer Society, Washington DC, 1999)
61.
W. Knight, Two heads are better than one (dual-core processors). IEE Rev. 51, 32–35 (2005)CrossRef
62.
P. Gepner, D. Fraser, M. Kowalik, R. Tylman, New multi-core intel xeon processors help design energy efficient solution for high performance computing, in Proceedings of the International Multiconference on Computer Science and Information Technology, 2009 (IMCSIT ’09), pp. 567–571, October 2009
63.
S. Borkar, Thousand core chips: a technology perspective, in Proceedings of the 44th Annual Design Automation Conference (DAC ’07), pp. 746–749 (ACM, New York, 2007)
64.
K. Asanovic, R. Bodik, J. Demmel, T. Keaveny, K. Keutzer, J. Kubiatowicz, N. Morgan, D. Patterson, K. Sen, J. Wawrzynek, D. Wessel, K. Yelick, A view of the parallel computing landscape. Commun. ACM 52, 56–67 (2009)CrossRef
65.
G. Martin, Multi-processor soc-based design methodologies using configurable and extensible processors. J. Signal Process. Syst. 53(1–2), 113–127 (2008)CrossRef
66.
Y.-K. Chen, C. Chakrabarti, S. Bhattacharyya, B. Bougard, Signal processing on platforms with multiple cores, part 1: overview and methodologies (from the guest editors). IEEE Signal Process. Mag. 26, 24–25 (2009)CrossRef
67.
68.
J. Goodacre, A. Sloss, Parallelism and the arm instruction set architecture. Computer 38, 42–50 (2005)CrossRef
69.
U. Kapasi, W. Dally, S. Rixner, J. Owens, B. Khailany, The imagine stream processor, in Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 282–288 (2002)
70.
71.
72.
W. Wolf, A. Jerraya, G. Martin, Multiprocessor system-on-chip (mpsoc) technology. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 27, 1701–1713 (2008)CrossRef
73.
R. Kumar, D.M. Tullsen, P. Ranganathan, N.P. Jouppi, K.I. Farkas, Single-isa heterogeneous multi-core architectures for multithreaded workload performance. SIGARCH Comput. Archit. News 32, 64 (2004)CrossRef
74.
R. Kumar, D. M. Tullsen, N. P. Jouppi, Core architecture optimization for heterogeneous chip multiprocessors, in Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT ’06), pp. 23–32 (ACM, New York, 2006)
75.
M. Hill, M. Marty, Amdahl’s law in the multicore era. Computer 41, 33–38 (2008)CrossRef
76.
F. Sun, S. Ravi, A. Raghunathan, N.K. Jha, Synthesis of application-specific heterogeneous multiprocessor architectures using extensible processors, in VLSID ’05: Proceedings of the 18th International Conference on VLSI Design Held Jointly with 4th International Conference on Embedded Systems Design, pp. 551–556 (IEEE Computer Society, Washington DC, 2005)
77.
R. Hameed, W. Qadeer, M. Wachs, O. Azizi, A. Solomatnikov, B.C. Lee, S. Richardson, C. Kozyrakis, M. Horowitz, Understanding sources of ineffciency in general-purpose chips. Commun. ACM 54, 85–93 (2011)CrossRef
78.
H. P. Hofstee, Power efficient processor architecture and the cell processor, in Proceedings of the 11th International Symposium on High-Performance Computer Architecture, pp. 258–262 (IEEE Computer Society, 2005)
79.
80.
81.
82.
83.
P. Flake, S. Davidmann, F. Schirrmeister, System-level exploration tools for mpsoc designs, in DAC ’06: Proceedings of the 43rd annual Design Automation Conference, pp. 286–287, (ACM, New York, 2006)
84.
G. Kahn, The semantics of a simple language for parallel programming, in Proceedings of the IFIP Congress on Information Processing ’74, pp. 471–475 (1974)
85.
E.A. Lee, D.G. Messerschmitt, Synchronous data flow. Proc. IEEE 75(9), 1235–1245 (1987)CrossRef
86.
W. Thies, M. Karczmarek, S.P. Amarasinghe, Streamit: a language for streaming applications, in Proceedings of the 11th International Conference on Compiler Construction, CC ’02, pp. 179–196 (Springer, 2002)
87.
A. Sangiovanni-Vincentelli, Quo vadis, sld? reasoning about the trends and challenges of system level design. Proc. IEEE 95, 467–506 (2007)CrossRef
88.
H. Guo, S. Parameswaran, Balancing system level pipelines with stage voltage scaling, in Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design, ISVLSI ’05 (2005)
89.
S. Carta, A. Alimonda, A. Pisano, A. Acquaviva, L. Benini, A control theoretic approach to energy-efficient pipelined computation in mpsocs, ACM Trans. Embedded Comput. Syst. Article id 27: 6(4), 28 (2007)
90.
A. Alimonda, S. Carta, A. Acquaviva, A. Pisano, L. Benini, A feedback-based approach to dvfs in data-flow applications. IEEE Trans. CAD Integr. Circ. Syst. 28(11), 1691–1704 (2009)CrossRef
91.
S. L. Shee, S. Parameswaran, Design methodology for pipelined heterogeneous multiprocessor system, in DAC ’07: Proceedings of the 44th Annual Conference on Design Automation, pp. 811–816 (2007)
92.
H. Javaid, A. Ignjatovic, S. Parameswaran, Rapid design space exploration of application specific heterogeneous pipelined multiprocessor systems. Trans. Comput. Aided Des. Integr. Circ. Syst. 29, 1777–1789 (2010)CrossRef
93.
I. Karkowski, H. Corporaal, Design of heterogenous multi-processor embedded systems: applying functional pipelining, in PACT ’97: Proceedings of the 1997 International Conference on Parallel Architectures and Compilation Techniques (IEEE Computer Society, 1997)
94.
M.I. Gordon, W. Thies, S. Amarasinghe, Exploiting coarse-grained task, data, and pipeline parallelism in stream programs. SIGPLAN Not. 41, 151–162 (2006)CrossRef
95.
H. Park, Y. Park, S. Mahlke, Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applications, in Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 42), pp. 370–380 (ACM, New York, 2009)
96.
M.A. Suleman, M.K. Qureshi, Khubaib, Y.N. Patt, Feedback-directed pipeline parallelism, in Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques (PACT ’10), pp. 147–156 (ACM, New York, 2010)
97.
4g applications, architectures, design methodology and tools for mpsoc, in DATE ’06: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 830–831 (European Design and Automation Association, Leuven, 2006)
98.
G. Goossens, Multi-asip socs: or how to design ultra-low power architectures for wireless and multi-media systems, in Proceedings of the 2007 International Symposium on System-on-Chip, p. 1, November 2007
99.
S. Verdoolaege, H. Nikolov, T. Stefanov, Pn: a tool for improved derivation of process networks. EURASIP J. Embedded Syst. 2007, 19 (2007)
100.
D. Cordes, A. Heinig, P. Marwedel, A. Mallik, Automatic extraction of pipeline parallelism for embedded software using linear programming, in Proceedings of the 2011 IEEE 17th International Conference on Parallel and Distributed Systems (ICPADS), pp. 699–706, December 2011
101.
M. Kudlur, S. Mahlke, Orchestrating the execution of stream programs on multicore platforms, in Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI ’08) (2008)
102.
M. Hashemi, S. Ghiasi, Throughput-driven synthesis of embedded software for pipelined execution on multicore architectures. ACM Trans. Embed. Comput. Syst. 8, 11:1–11:35 (2009)CrossRef
103.
S. M. Farhad, Y. Ko, B. Burgstaller, B. Scholz, Orchestration by approximation: mapping stream programs onto multicore architectures, in Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS ’11) (2011)
Metadaten
Titel
Introduction
verfasst von
Haris Javaid
Sri Parameswaran
Copyright-Jahr
2014
Buch
Pipelined Multiprocessor System-on-Chip for Multimedia

Print ISBN: 978-3-319-01112-7

Electronic ISBN: 978-3-319-01113-4

Copyright-Jahr: 2014

DOI
https://doi.org/10.1007/978-3-319-01113-4_1

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