nach oben

Erschienen in:

2024 | OriginalPaper | Buchkapitel

1. Introduction

verfasst von : Jinshan Yue

Erschienen in: High Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architecture

Verlag: Springer Nature Singapore

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config

KI-gestützte Suche

Aus

Abstract

Artificial Intelligence (AI) has promoted the development of modern society in many aspects [1], and will profoundly change human social life and the world [2].

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

über 102.000 Bücher
über 537 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Finance + Banking
Management + Führung
Marketing + Vertrieb
Maschinenbau + Werkstoffe
Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

über 67.000 Bücher
über 390 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Maschinenbau + Werkstoffe

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Nächstes Kapitel Basics and Research Status of Neural Network Processors

The concepts and calculation methods of performance and OPS are detailed in Sect. 2.2

LeCun Y, Bengio Y, Hinton G (2015) Deep learning. Nature 521(7553):436–444CrossRef

The State Council of the People’s Republic of China (2017) Development plan for the new generation of artificial intelligence, no 35

Dutton T (2018) An overview of national AI strategies

Deng J, Dong W, Socher R, Li L-J, Li K, Fei-Fei L (2009) ImageNet: a large-scale hierarchical image database. In: 2009 IEEE conference on computer vision and pattern recognition. IEEE, pp 248–255

Krizhevsky A, Sutskever I, Hinton GE (2012) ImageNet classification with deep convolutional neural networks. In: Advances in neural information processing systems, pp 1097–1105

Simonyan K, Zisserman A (2014) Very deep convolutional networks for large-scale image recognition. arXiv:1409.1556

Szegedy C, Liu W, Jia Y, Sermanet P, Reed S, Anguelov D, Erhan D, Vanhoucke V, Rabinovich A (2014) Going deeper with convolutions. In: Proceedings of the IEEE conference on computer vision and pattern recognition, pp 1–9

He K, Zhang X, Ren S, Sun J (2016) Deep residual learning for image recognition. In: Proceedings of the IEEE conference on computer vision and pattern recognition, pp 770–778

Huang G, Liu Z, Van Der Maaten L, Weinberger KQ (2017) Densely connected convolutional networks. In: Proceedings of the IEEE conference on computer vision and pattern recognition, pp 4700–4708

10.

Vaswani A, Shazeer N, Parmar N, Uszkoreit J, Jones L, Gomez AN, Kaiser Ł, Polosukhin I (2017) Attention is all you need. In: Proceedings of the 31st international conference on neural information processing systems, pp 6000–6010

11.

Goodfellow I, Pouget-Abadie J, Mirza M, Xu B, Warde-Farley D, Ozair S, Courville A, Bengio Y (2014) Generative adversarial nets. In: Advances in neural information processing systems, 27

12.

Silver D, Huang A, Maddison CJ, Guez A, Sifre L, Van Den Driessche G, Schrittwieser J, Antonoglou I, Panneershelvam V, Lanctot M et al (2016) Mastering the game of go with deep neural networks and tree search. Nature 529(7587):484–489

13.

Ltd. Askci Consulting Co. (2020) 2020–2025 China’s artificial intelligence chip industry outlook forecast and market research report

14.

Bianco S, Cadene R, Celona L, Napoletano P (2018) Benchmark analysis of representative deep neural network architectures. IEEE Access 6:64270–64277CrossRef

15.

Niu W, Ma X, Lin S, Wang S, Qian X, Lin X, Wang Y, Ren B (2020) PATDNN: achieving real-time DNN execution on mobile devices with pattern-based weight pruning. In: Proceedings of the 25th international conference on architectural support for programming languages and operating systems, pp 907–922

16.

NVIDIA A100 tensor core GPU (2021)

17.

JETSON NANO (2021)

18.

The 19th Central Committee of the Communist Party of China (2020) Proposal of the central committee of the communist party of China on formulating the 14th five year plan for national economic and social development and the long range goals for 2035. People’s Publishing House

19.

Chen T, Du Z, Sun N, Wang J, Wu C, Chen Y, Temam O (2014) DIANNAO: a small-footprint high-throughput accelerator for ubiquitous machine-learning. In: Proceedings of the 19th international conference on architectural support for programming languages and operating systems, pp 269–284

20.

Chen Y-H, Krishna T, Emer J, Sze V (2016) 14.5 Eyeriss: an energy-efficient reconfigurable accelerator for deep convolutional neural networks. In: 2016 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 262–264

21.

Bang S, Wang J, Li Z, Cao G, Sylvester D (2017) 14.7 A 288 \(\upmu \)w programmable deep-learning processor with 270 kB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence. In: 2017 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 250, 251

22.

Zhou S, Wu Y, Ni Z, Zhou X, Wen H, Zou Y (2016) Dorefa-net: Training low bitwidth convolutional neural networks with low bitwidth gradients. arXiv:1606.06160

23.

Rastegari M, Ordonez V, Redmon J, Farhadi A (2016) Xnor-net: ImageNet classification using binary convolutional neural networks. In: European conference on computer vision. Springer, pp 525–542

24.

Han S, Pool J, Tran J, Dally W (2015) Learning both weights and connections for efficient neural network. In: Advances in neural information processing systems, pp 1135–1143

25.

Wei W, Wu C, Yandan W, Yiran C, Hai L (2016) Learning structured sparsity in deep neural networks. Adv Neural Inf Process Syst 29:2074–2082

26.

Mao H, Han S, Pool J, Li W, Liu X, Wang Y, Dally WJ (2017) Exploring the granularity of sparsity in convolutional neural networks, pp 13–20

27.

Zhang T, Ye S, Zhang K, Tang J, Wen W, Fardad M, Wang Y (2018) A systematic DNN weight pruning framework using alternating direction method of multipliers. In: Proceedings of the European conference on computer vision (ECCV), pp 184–199

28.

Ding C, Liao S, Wang Y, Li Z, Liu N, Zhuo Y, Wang C, Qian X, Bai Y, Yuan G et al (2017) CirCNN: accelerating and compressing deep neural networks using block-circulant weight matrices. In: Proceedings of the 50th annual IEEE/ACM international symposium on microarchitecture. ACM, pp 395–408

29.

Moons B, Uytterhoeven R, Dehaene W, Verhelst M (2017) 14.5 ENVISION: a 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable convolutional neural network processor in 28 nm FDSOI. In: 2017 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 246–247

30.

Lee J, Kim C, Kang S, Shin D, Kim S, Yoo H-J (2018) UNPU: A 50.6 TOPS/W unified deep neural network accelerator with 1b-to-16b fully-variable weight bit-precision. In: 2018 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 218–220

31.

Zhang S, Du Z, Zhang L, Lan H, Liu S, Li L, Guo Q, Chen T, Chen Y (2016) Cambricon-x: an accelerator for sparse neural networks. In: The 49th annual IEEE/ACM international symposium on microarchitecture. IEEE, p 20

32.

Jorge A, Patrick J, Tayler H, Tor A, Jerger NE, Moshovos A (2016) Ineffectual-neuron-free deep neural network computing. In: International symposium on computer architecture, Cnvlutin

33.

Han S, Liu X, Mao H, Pu J, Pedram A, Horowitz MA, Dally WJ (2016) EIE: efficient inference engine on compressed deep neural network. In: 2016 ACM/IEEE 43rd annual international symposium on computer architecture (ISCA). IEEE, pp 243–254

34.

Parashar A, Rhu M, Mukkara A, Puglielli A, Venkatesan R, Khailany B, Emer J, Keckler SW, Dally WJ (2017) SCNN: an accelerator for compressed-sparse convolutional neural networks. In: 2017 ACM/IEEE 44th annual international symposium on computer architecture (ISCA). IEEE, pp 27–40

35.

Zimmer B (2021) Emulating large machine learning accelerators with small research chips. In: IEEE international solid-state circuits conference (ISSCC) forum. IEEE

36.

Kozyrakis CE, Perissakis S, Patterson D, Anderson T, Asanovic K, Cardwell N, Fromm R, Golbus J, Gribstad B, Keeton K et al (1997) Scalable processors in the billion-transistor era: IRAM. Computer 30(9):75–78

37.

Maya G, Bill H, Ken I (1995) Processing in memory: the terasys massively parallel PIM array. Computer 28(4):23–31

38.

Elliott D, Stumm M, Snelgrove M (1997) Computational RAM: the case for SIMD computing in memory. In: Workshop on mixing logic and DRAM: chips that compute and remember at ISCA, vol 97

39.

Yamauchi T, Hammond L, Olukotun K (1997) A single chip multiprocessor integrated with DRAM. In: Workshop on mixing logic and DRAM, held at the 24th international symposium on computer architecture

40.

Chang M-F, Wu C-W, Kuo C-C, Shen S-J, Lin K-F, Yang S-M, King Y-C, Lin C-J, Chih Y-D (2012) A 0.5 V 4 MB logic-process compatible embedded resistive RAM (ReRAM) in 65 nm CMOS using low-voltage current-mode sensing scheme with 45 ns random read time. In: 2012 IEEE international solid-state circuits conference. IEEE, pp 434–436

41.

Prezioso M, Merrikh-Bayat F, Hoskins BD, Adam GC, Likharev KK, Strukov DB (2015) Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature 521(7550):61–64

42.

Su F, Chen W-H, Xia L, Lo C-P, Tang T, Wang Z, Hsu K-H, Cheng M, Li J-Y, Xie Y et al (2017) A 462GOPs/J RRAM-based nonvolatile intelligent processor for energy harvesting IoE system featuring nonvolatile logics and processing-in-memory. In: 2017 symposium on VLSI technology. IEEE, pp T260–T261

43.

Chen W-H, Li K-X, Lin W-Y, Hsu K-H, Li P-Y, Yang C-H, Xue C-X, Yang E-Y, Chen Y-K, Chang Y-S et al (2018) A 65 nm 1 MB nonvolatile computing-in-memory ReRAM macro with sub-16 ns multiply-and-accumulate for binary DNN AI edge processors. In: 2018 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 494–496

44.

Biswas A, Chandrakasan AP (2018) Conv-RAM: an energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications. In: 2018 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 488–490

45.

Khwa W-S, Chen J-J, Li J-F, Si X, Yang E-Y, Sun X, Liu R, Chen P-Y, Li Q, Yu S et al (2018) A 65 nm 4 kB algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8 TOPS/W fully parallel product-sum operation for binary DNN edge processors. In: 2018 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 496–498

46.

Si X, Chen J-J, Tu Y-N, Huang W-H, Wang J-H, Chiu Y-C, Wei W-C, Wu S-Y, Sun X, Liu R et al (2019) 24.5 A twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning. In: 2019 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 396–398

47.

Yang J, Kong Y, Wang Z, Liu Y, Wang B, Yin S, Shi L (2019) 24.4 sandwich-RAM: an energy-efficient in-memory BWN architecture with pulse-width modulation. In: 2019 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 394–396

48.

Su J-W, Si X, Chou Y-C, Chang T-W, Huang W-H, Tu Y-N, Liu R, Lu P-J, Liu T-W, Wang J-H et al (2020) 15.2 A 28 nm 64 kB inference-training two-way transpose multibit 6T SRAM compute-in-memory macro for AI edge chips. In: 2020 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 240–242

49.

Si X, Tu Y-N, Huanq W-H, Su J-W, Lu P-J, Wang J-H, Liu T-W, Wu S-Y, Liu R, Chou Y-C et al (2020) 15.5 A 28 nm 64 kB 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips. In: 2020 IEEE international solid-state circuits conference (ISSCC). IEEE, pp 246–248

50.

Guo R, Liu Y, Zheng S, Wu S-Y, Ouyang P, Khwa W-S, Chen X, Chen J-J, Li X, Liu L et al (2019) A 5.1 pJ/neuron 127.3 \(\upmu \)s/inference RNN-based speech recognition processor using 16 computing-in-memory SRAM macros in 65 nm CMOS. In: 2019 symposium on VLSI circuits. IEEE, pp C120, C121

51.

Li S, Niu D, Malladi KT, Zheng H, Brennan B, Xie Y (2017) DRISA: a DRAM-based reconfigurable in-situ accelerator. In: 2017 50th annual IEEE/ACM international symposium on microarchitecture (MICRO). IEEE, pp 288–301

52.

Seshadri V, Lee D, Mullins T, Hassan H, Boroumand A, Kim J, Kozuch MA, Mutlu O, Gibbons PB, Mowry TC (2017) Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology. In: 2017 50th annual IEEE/ACM international symposium on microarchitecture (MICRO). IEEE, pp 273–287

53.

Guo X, Merrikh Bayat F, Prezioso M, Chen Y, Nguyen B, Do N, Strukov DB (2017) Temperature-insensitive analog vector-by-matrix multiplier based on 55 nm NOR flash memory cells. In: 2017 IEEE custom integrated circuits conference (CICC). IEEE, pp 1–4

54.

Guo X, Merrikh Bayat F, Bavandpour M, Klachko M, Mahmoodi MR, Prezioso M, Likharev KK, Strukov DB (2017) Fast, energy-efficient, robust, and reproducible mixed-signal neuromorphic classifier based on embedded NOR flash memory technology. In: 2017 IEEE international electron devices meeting (IEDM). IEEE, pp 6–5

55.

Ali K, Kai N, Wilbert VDH, Suman D, Arijit R (2020) Ferroelectronics for edge intelligence. IEEE Micro 40(6):33–48

56.

Khan AI, Keshavarzi A, Datta S (2020) The future of ferroelectric field-effect transistor technology. Nat Electron 3(10):588–597

57.

Manuel LG, Abu S, Roland M, Matteo M, Heiner G, Tomas T, Costas B, Alessandro C, Evangelos E (2018) Mixed-precision in-memory computing. Nat Electron 1(4):246–253

58.

Shi Y, Oh S, Huang Z, Lu X, Kang SH, Kuzum D (2020) Performance prospects of deeply scaled spin-transfer torque magnetic random-access memory for in-memory computing. IEEE Electron Dev Lett 41(7):1126–1129

Titel: Introduction
verfasst von: Jinshan Yue
Verlag: Springer Nature Singapore
Buch: High Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architecture
Print ISBN: 978-981-9734-76-4

Electronic ISBN: 978-981-9734-77-1

Copyright-Jahr: 2024
DOI: https://doi.org/10.1007/978-981-97-3477-1_1