Anzeige
Erschienen in:
2011 | OriginalPaper | Buchkapitel
IO-Aware Custom Instruction Exploration for Customizing Embedded Processors
verfasst von : Amir Yazdanbakhsh, Mostafa E. Salehi
Erschienen in: Future Information Technology
Verlag: Springer Berlin Heidelberg
Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.
Wählen Sie Textabschnitte aus um mit Künstlicher Intelligenz passenden Patente zu finden. powered by
Markieren Sie Textabschnitte, um KI-gestützt weitere passende Inhalte zu finden. powered by
This paper describes a methodology for identifying custom instructions for critical code segments of embedded applications, considering the available data bandwidth constraint between custom logic and the base processor. Our approach enables designers to optionally constrain the number of input and output operands for custom instructions to reach the acceptable performance. We describe a design flow to establish the desired performance. We study the effects of input/output constraints and registerfile read/write ports on overall speedup of the system. Our experiments show that, in most cases, the solutions with the highest merit are not identified with relaxed input/output constraints. Results for packet-processing benchmarks covering cryptography, lookup, and classification show speed-up up to 40%.