Ausgabe 1/2017
Inhalt (12 Artikel)
Open Access
Test Planning for Core-based Integrated Circuits under Power Constraints
Breeta SenGupta, Dimitar Nikolov, Urban Ingelsson, Erik Larsson
A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits
I. Wali, B. Deveautour, Arnaud Virazel, A. Bosio, P. Girard, M. Sonza Reorda
Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s Using Universal Rad-SPICE MOSFET Model
Konstantin O. Petrosyants, Lev M. Sambursky, Igor A. Kharitonov, Boris G. Lvov
A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms
Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey
On the Consolidation of Mixed Criticalities Applications on Multicore Architectures
Stefano Esposito, Massimo Violante
A HW/SW Cross-Layer Approach for Determining Application-Redundant Hardware Faults in Embedded Systems
Christian Bartsch, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz
An Efficient Reverse Engineering Hardware Trojan Detector Using Histogram of Oriented Gradients
Abdurrahman A. Nasr, Mohamed Z. Abdulmageed
Golden-Free Hardware Trojan Detection with High Sensitivity Under Process Noise
Tamzidul Hoque, Seetharam Narasimhan, Xinmu Wang, Sanchita Mal-Sarkar, Swarup Bhunia
High Speed Energy Efficient Static Segment Adder for Approximate Computing Applications
R . Jothin, C. Vasanthanayaki
Fast and Automated Electromigration Analysis for CMOS RF PA Design
Junjie Gu, Haipeng Fu, Weicong Na, Qijun Zhang, Jianguo Ma