Ausgabe 3/2016
Inhalt (15 Artikel)
Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures
Igor Aleksejev, Sergei Devadze, Artur Jutman, Konstantin Shibin
Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing
Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada
Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits
Maksim Jenihhin, Giovanni Squillero, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik, Matteo Sonza Reorda, Leticia Bolzani Poehls, Raimund Ubar, Guilherme Cardoso Medeiros
A Fast Statistical Soft Error Rate Estimation Method for Nano-scale Combinational Circuits
Mohsen Raji, Behnam Ghavami
Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability
Hector Villacorta, Jaume Segura, Victor Champac
NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach for Increasing Circuits’ Life Time
T. Copetti, G. Cardoso Medeiros, L. Bolzani Poehls, F. Vargas
Security Path: An Emerging Design Methodology to Protect the FPGA IPs Against Passive/Active Design Tampering
Sharareh Zamanzadeh, Ali Jahanian
Side-Channel Information Characterisation Based on Cascade-Forward Back-Propagation Neural Network
Ehsan Saeedi, Md Selim Hossain, Yinan Kong
Automatic Feature Selection of Hardware Layout: A Step toward Robust Hardware Trojan Detection
Abdurrahman A. Nasr, Mohamed Z. Abdulmageed
High Performance Significance Approximation Error Tolerance Adder for Image Processing Applications
R. Jothin, C. Vasanthanayaki
An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology
Qingyu Chen, Haibin Wang, Li Chen, Lixiang Li, Xing Zhao, Rui Liu, Mo Chen, Xuantian Li
A New Capacitance-to-Frequency Converter for On-Chip Capacitance Measurement and Calibration in CMOS Technology
Dongdi Zhu, Jiongjiong Mo, Shiyi Xu, Yongheng Shang, Zhiyu Wang, Zhengliang Huang, Faxin Yu