Journal of Electronic Testing

Editorial

Vishwani D. Agrawal

Test Technology Newsletter

Optimization of Test Wrapper for TSV Based 3D SOCs

Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman

A Novel Approach for Diagnosis of Analog Circuit Fault by Using GMKL-SVM and PSO

Chaolong Zhang, Yigang He, Lifen Yuan, Wei He, Sheng Xiang, Zhigang Li

Reliability Analysis of Fault-Tolerant Bus-Based Interconnection Networks

Fathollah Bistouni, Mohsen Jahanshahi

Analyzing Vulnerability of Asynchronous Pipeline to Soft Errors: Leveraging Formal Verification

Faiq Khalid Lodhi, Syed Rafay Hasan, Osman Hasan, Falah Awwad

Current-Based Testing, Modeling and Monitoring for Operational Deterioration of a Memristor-Based LUT

T. Nandha Kumar, Haider A. F. Almurib, Fabrizio Lombardi

Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing

Michihiro Shintani, Takumi Uezono, Kazumi Hatayama, Kazuya Masu, Takashi Sato

A Comprehensive FPGA-Based Assessment on Fault-Resistant AES against Correlation Power Analysis Attack

Jaya Dofe, Hoda Pahlevanzadeh, Qiaoyan Yu

CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator

Kuen-Wei Yeh, Jiun-Lang Huang, Laung-Terng Wang

Test Data Compression for System-on-chip using Flexible Runs-aware PRL Coding

Haiying Yuan, Zijian Ju, Xun Sun, Kun Guo, Xiuyu Wang

A Novel Compact Model for On-Chip Vertically-Coiled Spiral Inductors

Bing Hou, Tong Liu, Jun Liu, Junli Chen, Faxin Yu, Wenbo Wang