Languages, Design Methods, and Tools for Electronic System Design

Synchronous languages, such as the recently proposed SCCharts language, have been designed for the rigorous specification of real-time systems. Their sound semantics, which build on an abstraction from physical execution time, make these languages appealing, in particular for safety-critical systems. However, they traditionally lack built-in support for physical time. This makes it rather cumbersome to express things like timeouts or periodic executions within the language.

We here propose several mechanisms to reconcile the synchronous paradigm with physical time. Specifically, we propose extensions to the SCCharts language to express clocks and execution periods within the model. We draw on several sources, in particular timed automata, the Clock Constraint Specification Language, and the recently proposed concept of dynamic ticks. We illustrate how these extensions can be mapped to the SCChart language core, with minimal requirements on the runtime system, and we argue that the same concepts could be applied to other synchronous languages such as Esterel, Lustre, or SCADE.

Modeling Cyber-Physical Systems requires aggregating semantics and languages tailored to different specific domains, while simulating these systems requires integrating different tools and technologies. Academy and Industry are working to define standard interfaces allowing to facilitate such integration. The Functional Mockup Interface (FMI) standard is one of the most promising tools produced by this effort. It allows to easily export and integrate heterogeneous models. However, the standard still shows some weaknesses. In particular, it still does not provide a proper support for describing discrete-event systems.

In this chapter we analyze the current standard and its recently proposed extensions. In particular, we focus on its shortcomings when dealing with discrete models. Then, we present a systematic approach exploiting the features of the current standards to mitigate such limitations. The approach is based on two concepts: (1) exposing the internal time of each component and (2) exploiting the newly exposed information to implement temporal decoupling. The combination of these two concepts allows to optimize the coordination algorithms by reducing the number of synchronization points, thus moving the simulation from cycle- to transaction-accurate. The impact of these optimizations is measured on a set of benchmarks having different tread-offs of computation and control. Finally, we analyze some possible improvements that may be integrated in the future updates of the standard.

The Internet of Things (IoT) enables connectivity between devices, thereby allowing them to interact with each other. A recurring problem is the emergence of siloed IoT platforms due to proprietary standards. Recently, the World Wide Web Consortium (W3C) proposed a human-readable and machine-understandable format called Thing Description (TD). It allows to uniformly describe device and service interfaces of different IoT standards with syntactic and semantic information, and hence enables semantic interoperability. However, describing the sequential behavior of devices, which is essential for many cyber-physical systems, is not covered. In this paper, we extend our initial contribution of describing such sequential behavior as an extension within TDs, thereby increasing their semantic expressiveness through possible, valid state transitions. This enables safe and desired operation of devices as well as scalability by modeling systems as sequential compositions of Things. We show in a case study that previously unmodelable behavior can now be expressed and the overall manual intervention requirements of the state-of-the-art implementations can be significantly reduced.

This overview chapter summarizes the content of a tutorial given at the 2018 edition of the Forum on Specification and Design Languages. The aim of the tutorial was to introduce the technology of microfluidic devices, which gained significant interest in the recent past, as well as corresponding design challenges to a community focused on design automation and corresponding specification/design languages. By this, the overview presents a starting point for researchers and engineers interested in getting involved in this area.

NBTI is becoming one of the major circuit reliability issues in nano-scale technologies. BTI can cause a threshold voltage shift in CMOS devices and consequently increase circuit delay. This paper proposed a novel ageing aware approach to improve circuit’s lifetime. The vulnerable circuit paths against ageing effects are isolated. In addition, minimum area overhead is consumed by adopting proposed synthesis algorithm. The simulation results show that the proposed approach can save up to 67.7% area compared with the conventional over-design technique.

IEEE SystemC is one of the most popular standards for system level design. With the Recoding Infrastructure for SystemC (RISC), a SystemC model can be executed at segment level in parallel. Although the parallel simulation is generally faster than its sequential counterpart, any data conflict among segments reduces the simulation speed significantly. In this paper, we propose for RISC users a coding guideline that increases the granularity of segments, so that the level of parallelism in the design increases and higher simulation speed becomes possible. Our experimental results show that a maximum speedup of over 6.0x is achieved on an 8-core processor, which is 1.7 times faster than parallel simulation without the coding guideline.

Internet-of-Things (IoT) opens a new world of possibilities for both personal and industrial applications. At the heart of an IoT device, the processor is the core component. Hence, as an open and free instruction set architecture RISC-V is gaining huge popularity for IoT. A large ecosystem is available around RISC-V, including various RTL implementations at one end and high-speed instruction set simulators (ISSs) at the other end. These ISSs facilitate functional verification of RTL implementations as well as early SW development to some extent. However, being designed predominantly for speed, they can hardly be extended to support further system-level use cases such as design space exploration, power/timing/performance validation, or analysis of complex HW/SW interactions. In this paper, we propose and implement the first RISC-V based Virtual Prototype (VP) with the goal of filling this gap. We provide a RISC-V RV32IM core, a PLIC-based interrupt controller, and an essential set of peripherals together with SW debug capabilities. The VP is designed as extensible and configurable platform with a generic bus system and implemented in standard-compliant SystemC and TLM-2.0. The latter point is very important, since it allows to leverage cutting-edge SystemC-based modeling techniques needed for the mentioned use cases. Our VP allows a significantly faster simulation compared to RTL, while being more accurate than existing ISSs. Finally, our RISC-V VP is fully open source to help expanding the RISC-V ecosystem and stimulating further research and development.

Traditional modeling languages and simulators are still separated from formal verification languages and tools. The main reason for this is that formal verification algorithms require a formal model of a system to verify its behavior. However, the automatic generation of such model requires a separate, dedicated compiler. This paper shows an approach how to use the existing simulator to generate a formal model of a system without using yet another compiler, intermediate language or tool. The approach is based on generation of AADD and BDD for symbolic simulation and it is integrated in SystemC AMS modeling language and simulator.

We discuss how separate compilation and usage of structured data can be achieved in a synchronous imperative programming language for embedded systems. Our focus is on the practical aspects of these questions regarding expressiveness in programs as well as causality analysis and code generation. The approach is illustrated by means of examples written in our new language Blech. In particular, we revisit the stopwatch example from the literature to discuss causality, separate compilation, and other aspects of software engineering in more depth. This is an extended version of a previously published article.