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Erschienen in:
Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections Kapitel lesen Erstes Kapitel lesen

2011 | OriginalPaper | Buchkapitel

7. Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study

verfasst von : Rudy Beraha, Isask’har Walter, Israel Cidon, Avinoam Kolodny

Erschienen in: Low Power Networks-on-Chip

Verlag: Springer US

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Abstract

In this chapter, we examine the design process of a network on-chip (NoC) for a high-end commercial system on-chip (SoC) application. We present several design choices and focus on the power optimization of the NoC while achieving the required performance. Our design steps include module mapping and allocation of customized capacities to links. Unlike previous studies, in which point-to-point, per-flow timing constraints were used, we demonstrate the importance of using the application end-to-end traversal latency requirements during the optimization process. In order to evaluate the different alternatives, we report the synthesis results of a design that meets the actual throughput and timing requirements of the commercial SoC. According to our findings, the proposed technique offers up to 40% savings in the total router area, 49% savings in the inter-router wiring area, and a 16% reduction of total power for our target router architecture.

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Vorheriges Kapitel Adaptive Data Compression for Low-Power On-Chip Networks
Nächstes Kapitel Design and Analysis of NoCs for Low-Power 2D and 3D SoCs
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Metadaten
Titel
Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study
verfasst von
Rudy Beraha
Isask’har Walter
Israel Cidon
Avinoam Kolodny
Copyright-Jahr
2011
Verlag
Springer US
Buch
Low Power Networks-on-Chip

Print ISBN: 978-1-4419-6910-1

Electronic ISBN: 978-1-4419-6911-8

Copyright-Jahr: 2011

DOI
https://doi.org/10.1007/978-1-4419-6911-8_7

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