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Über dieses Buch

Legacy Data: A Structured Methodology For Device Migration in DSM Technology deals with the migration of existing hard IP from one technology to another using repeatable procedures. The challenge of hard IP migration is not simply an EDA problem but rather a client application specification problem. It requires a deep understanding of the process technologies, EDA tools (and their interfaces) and target applications.
Legacy Data: A Structured Methodology For Device Migration in DSM Technology is unique in that there are currently no reference books focused on legacy data reuse, especially for hard IP. This book will allow CAD practitioners to quickly develop methodologies that capitalize on the large volumes of legacy data available within a company today. It details the issues of developing a structured methodology, building verification test benches, and validating the final physical design.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Introduction

Abstract
As an independent consultant providing design and CAD methodology support, I have participated in a wide variety of chip tapeouts. These ranged from small analog chips, to RF chips to large microprocessor products to multi-million gate mixed signal SOCs.
Pallab Chatterjee

Chapter 2. What is Legacy Data?

Abstract
Legacy data is generally thought of as data from a previous design that has to be identified and used again.
Pallab Chatterjee

Chapter 3. Reasons for Data Migration

Abstract
Over the last few years the reasons behind data migration have changed. Historically the driving basis for data migration was the creation and qualification of a second source for manufacturing of a product. Shortened life cycles and shortened time to market for the end chips have now made the “second source” requirements for most products obsolete.
Pallab Chatterjee

Chapter 4. New Rules for DSM Flows

Abstract
New process options have posed a new problem in the selection of target technologies for migrated data. The discussions that follow are targeted to address like processes and are intended to cover the additional details of device change migration. Some of these device change migrations include traditional CMOS designs being ported to a SiGe process technology. Some of these process selection issues are:
1.
Device geometries
 
2.
Wafer type and substrate
 
3.
Isolation technique
 
4.
Operating voltage
 
5.
Process designs rules
 
6.
Device performance
 
7.
Interconnect options
 
8.
Memory techniques
 
9.
OPC masking techniques
 
Pallab Chatterjee

Chapter 5. Structured Methodology

Abstract
Legacy data migration can be optimally performed if a structured sequential flow is applied. The flow will have the steps of the sequence detailed in subsequent chapters. A flow chart of the methodology, overview of the flow and background on each of the steps is the basis of this chapter.
Pallab Chatterjee

Chapter 6. Screening Criteria for Blocks

Abstract
One of the most important steps in the legacy migration process is the screening and selection of a design block for reuse.
Pallab Chatterjee

Chapter 7. Process Compatibility

Abstract
Modern DSM processes have a lot more in common with processes at the start of the semiconductor industry than they have with recent single-tub bulk CMOS processes. Process issues that have long been ignored are now critical to both the correct design but also correct selection of the process. Masking correction methods like OPC have resurfaced as correction solutions for the first time since the metal gate era.
Pallab Chatterjee

Chapter 8. Test Bench Requirements

Abstract
The test bench is one of the most critical pieces of the legacy migration puzzle. It provides the list of inputs and expected outputs for all aspects of the legacy block. As such, it is the piece of the puzzle that let the engineering know when he has successfully completed the re-engineering task or has to keep working on it. Without the availability of a test bench, the design block cannot be re-engineered for reuse.
Pallab Chatterjee

Chapter 9. Block Identification

Abstract
Hierarchy is a design feature that is required for DSM designs due the complexity of the technology and magnitude of the design content. A great deal of this hierarchy is from hard IP and soft IP dedicated function RTL modules. Tool changes and methodology changes in sub 150nm technologies requires a much more rigid observation of the rules of hierarchy than in previous process technologies. As a result, the migration of blocks under the new constraints requires some modification and selection to the design data prior to reuse.
Pallab Chatterjee

Chapter 10. Design Retargeting

Abstract
Design retargeting is the actual engineering work to redesign the legacy block for being used in a new process and circuit application.
Pallab Chatterjee

Chapter 11. Design Validation

Abstract
Design validation is the task of interpreting if the new design has been successfully re-targeted for the new process. So far in the methodology, we have selected a block for migration, identified a compatible target process, identified the test bench for the design, determined the relevant design views were available to perform the migration and then performed the engineering re-design task on the block in a hierarchical fashion. This next task is to review the results of the re-design in the context of “does it pass the test bench”, “will it work in the new application and process” and “is it the new design that we want”?
Pallab Chatterjee

Chapter 12. Physical Design Migration

Abstract
Once the new netlist is ready and sized, and the design has been validated to be correct, then the physical design migration can begin. The physical migration flow is actually very straight forward as there are only a few options available for rebuild of the data. This chapter will outline and review the alternatives available for data reconstruction.
Pallab Chatterjee

Chapter 13. Post Layout Validation

Abstract
The area of post layout validation deals with the qualification of the design after the physical design is completed. The relevant aspects of the validation procedure fall into the following categories:
  • Design Rule Checking - DRC
  • Layout vs. Schematic - LVS
  • Power Analysis - IR Drop
  • Noise Analysis and Coupling - Signal Integrity
  • RC extraction for STA & for device simulation
Pallab Chatterjee

Chapter 14. Full Chip Verification

Abstract
Once a legacy data block has gone through the flow to allow it be available for new SOC design, it has to be setup properly for use. As is obvious at this point in the book, the nine step flow is not a quick one. A great deal of automation can be incorporated to reduce the manpower associated with the tasks, but the sheer quantity of data that is required to be created is the gating factor. In the maximally automated flow, the machine time for simulation, creation, and validation is about a factor of 10 longer than the operator time manning those steps.
Pallab Chatterjee

Backmatter

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