Lightweight Low-Power U-Net Architecture for Semantic Segmentation

The U-Net is a popular deep-learning model for semantic segmentation tasks. This paper describes an implementation of the U-Net architecture on FPGA (Field Programmable Gate Array) for real-time image segmentation. The proposed design uses a parallel-pipelined architecture to achieve high throughput and also focuses on addressing the resource and power constraints in edge devices by compressing CNN (Convolutional Neural Networks) models and improving hardware efficiency. To this end, we propose a pruning technique based on parallel quantization that reduces weight storage requirements by quantizing U-Net layers into a few segments, which in turn leads to the light weight of the U-Net model. The system requires \(\approx 1.5Mb\) of memory for storing weights. The Electron Microscopy Dataset and BraTs Dataset has demonstrated the proposed U-Net architecture, achieving an Intersection over Union (IoU) of 90.31% and 94.1% when utilizing 4-bit quantized weights. Additionally, we designed a shift-based U-Net accelerator that replaces multiplications with simple shift operations, further improving efficiency. The proposed U-Net architecture achieves a 3.5 \(\times\) reduction in power consumption and a 35% reduction in area compared to previous architectures. To further reduce power consumption, we omit the computation for zero weights. Overall, the present work puts forward an effective method for optimizing CNN models in edge devices while meeting their computational and power constraints.