An Efficient Timing and Clock Tree Aware Placement Flow with Multibit Flip-Flops for Power Reduction

Multibit flip-flops (MBFFs) approach have been discussed with significant interest in the literature as the promising way to minimize the power consumption of the clock network in the modern System on Chip (SoC) designs. However, in real designs with complex architectures, MBFFs approach without the full awareness of placement and clock tree information may adversely affect the design attributes. This includes heavy congestion post clock tree synthesis (CTS), long wire-lengths leading to higher voltage drop and timing violations. This paper introduces a novel placement methodology, integrated with existing electronic design automation (EDA) flow and tools, for MBFF generation with prerequisite knowledge of clock tree architecture. In addition, an algorithm for minimizing the clock insertion delay (CID) of the design is proposed. The algorithm reduces the CID by identifying the clock tree nets and the clock tree sinks which violate the CID at the early CTS stage. The proposed methodology is validated on two different designs which are complex and target real applications. The proposed methodology leads to 50.46% and 37.7% reduction in flip-flop power consumption for design I and II, respectively. Furthermore, the core density has improved by 12.8% and 9.8% for design I and II, respectively. An average reduction of 9.2% in the CID validates the superiority of the proposed algorithm over existing algorithm.