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A novel time-based low-power pipeline analog to digital converter

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Abstract

A new power reduction technique for analog-to-digital converters is proposed in this paper. A novel current-mode algorithm which uses time to perform analog-to-digital conversion has been described and a 12 bit 100-ksample/s time-based pipeline analog to digital converter has been designed and simulated in standard 90-nm CMOS technology based on introduced structure. Employed circuit techniques include a continues-time comparator, bottom plate sampling, digital correction and a state machine. A time based-mechanism has been used for subtraction and amplification. Simulation results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio of 69.8 dB, a peak spurious-free dynamic range of 75 dB, a total harmonic distortion of 73 dB, and a peak integral nonlinearity of 0.85 least significant bits. The total power dissipation is 90 μW from a 3-V supply.

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Authors and Affiliations

  1. Microelectronic and Microsensor Research Laboratory, Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran

    Mohammad Hossein Zarifi & Javad Frounchi

  2. Electrical and Computer Engineering Department, University of California, Los Angeles, CA, USA

    Shahin Farshchi & Jack W. Judy

Authors
  1. Mohammad Hossein Zarifi
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  2. Javad Frounchi
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  3. Shahin Farshchi
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  4. Jack W. Judy
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Correspondence to Mohammad Hossein Zarifi.

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Zarifi, M.H., Frounchi, J., Farshchi, S. et al. A novel time-based low-power pipeline analog to digital converter. Analog Integr Circ Sig Process 62, 281–289 (2010). https://doi.org/10.1007/s10470-009-9346-2

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  • DOI: https://doi.org/10.1007/s10470-009-9346-2

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