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FPGA implementation of high-speed neural network for power amplifier behavioral modeling

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Abstract

In this paper, a high-speed pipelined architecture of dynamic neural network is proposed for power amplifier behavioral modeling. This architecture is implemented on field programmable gate array (FPGA) using Xilinx system generator and Virtex-6 FPGA ML605 Evaluation Kit. The novelty of the proposed architecture is that it provides higher operating frequency, lower output latency, and less required resources. These improvements are obtained by reducing the bit-width data and by efficiently redistributing the inserted pipelining delays. The new pipelined architecture is evaluated and compared to the conventional and pseudo-conventional ones in terms of the resource utilization, the maximum operating frequency, and the modeling performances using the 16-QAM modeled test signal. This architecture is verified using JTAG hardware co-simulation both for single step and free-running clock modes.

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Authors and Affiliations

  1. Department of Engineering, Université du Québec à Rimouski, 300, allée des Ursulines, Rimouski, QC, G5L 3A1, Canada

    Mohammed Bahoura

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  1. Mohammed Bahoura
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Correspondence to Mohammed Bahoura.

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Bahoura, M. FPGA implementation of high-speed neural network for power amplifier behavioral modeling. Analog Integr Circ Sig Process 79, 507–527 (2014). https://doi.org/10.1007/s10470-014-0263-7

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  • DOI: https://doi.org/10.1007/s10470-014-0263-7

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