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Low Power Circuit and System Design Hierarchy and Thermal Reliability of Tunnel Field Effect Transistor

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Abstract

Tunnel FET is one of the promising devices advocated as a replacement of conventional MOSFET to be used for low power applications. Temperature is an important factor affecting the performance of circuits or system, so temperature associated reliability issues of double gate Tunnel FET and its impact on essential circuit design components have been addressed here. The temperature reliability investigation is based on double gate Tunnel FET, containing Si1-xGe x /Si, source/channel and HfO2 high-k gate dielectric material. During investigation, it has been found that at high temperature application range ~ 300 K - to - 600 K,the Tunnel FET device design parameters exhibit weak temperature dependency with switching current (ION), while the off-state current (IOFF) is slightly varying ~10−17A/μm-to-10−10A/μm. In addition, the impact of temperature on various device design element such as VTH(i.e.,switching voltage),on-current (ION), off-current (IOFF), switching ratio (ION/IOFF) and average subthreshold slope (i.e., SSavg), ambipolar current (IAMB) have been done in this research work.The essential circuit design components for digital and analog/RF applications, such as current amplification factor(gm) and its derivative (gm’),the C-V components of device design, Cgg, Cgd and Cgs, cut - off frequency (ƒT) and gain band width (GBW) product have deeply investigated. In conclusion, the obtained results show that the designed double gate Tunnel FET device configuration and its circuit design components are suitable for ultra-low power circuit,system applications and reliable for hazardous temperature environment.

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References

  1. Zhao Y, Liang Z, Huang Q, Chen C, Yang M, Sun Z, Zhu K, Wang H, Liu S, Liu T, Peng Y (2019) A novel negative capacitance tunnel FET with improved subthreshold swing and nearly non-hysteresis through hybrid modulation. IEEE Electron Device Letters 40(6):989–992. https://doi.org/10.1109/LED.2019.2909410

    Article  CAS  Google Scholar 

  2. Ionescu AM, Riel H (2011) Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479(7373):329–337. https://doi.org/10.1038/nature10679

    Article  CAS  PubMed  Google Scholar 

  3. Guo PF, Yang LT, Yang Y, Fan L, Han GQ, Samudra GS, Yeo YC (2009) Tunneling field-effect transistor: effect of strain and temperature on tunneling current. IEEE Electron Device Letters 30(9):981–983. https://doi.org/10.1109/LED.2009.2026296

    Article  CAS  Google Scholar 

  4. Bordallo, C.C., Martino, J.A., Agopian, P.G., Rooyackers, R., Vandooren, A., Thean, A., Simoen, E. and Claeys, C., 2015. Analysis of analog parameters in NW-TFETs with Si and SiGe source composition at high temperatures. In 2015 30th symposium on microelectronics technology and devices (SBMicro) (pp. 1-4). IEEE. doi: https://doi.org/10.1109/SBMicro.2015.7298148

  5. Bentrcia T, Djeffal F, Ferhati H, Dibi Z (2020) A comparative study on scaling capabilities of Si and SiGe nanoscale double gate tunneling FETs. Silicon 12(4):945–953. https://doi.org/10.1007/s12633-019-00190-

    Article  CAS  Google Scholar 

  6. Haddara, Y.M., Ashburn, P. and Bagnall, D.M., 2017. Silicon-germanium: properties, growth and applications. Springer handbook of electronic and photonic materials, pp.1-1. DOIhttps://doi.org/10.1007/978-3-319-48933-9_22

  7. Rahi SB, Asthana P, Gupta S (2017) Heterogate junctionless tunnel field-effect transistor: future of low-power devices. J Comput Electron 16(1):30–38. https://doi.org/10.1007/s10825-016-0936-9

    Article  CAS  Google Scholar 

  8. Rahi SB, Ghosh B, Bishnoi B (2015) Temperature effect on hetero structure junctionless tunnel FET. Journal of semiconductors 36(3):034002. https://doi.org/10.1088/1674-4926/36/3/034002

    Article  CAS  Google Scholar 

  9. Barboni L, Siniscalchi M, Sensale-Rodriguez B (2015) TFET-based circuit design using the transconductance generation efficiency ${g} _ {m}/{I} _ {d} $ method. IEEE Journal of the Electron Devices Society 3(3):208–216. https://doi.org/10.1109/JEDS.2015.2412118

    Article  Google Scholar 

  10. Sedighi B, Hu XS, Liu H, Nahas JJ, Niemier M (2014) Analog circuit design using tunnel-FETs. IEEE transactions on circuits and systems I: regular papers 62(1):39–48. https://doi.org/10.1109/TCSI.2014.2342371

    Article  Google Scholar 

  11. Lu H, Paletti P, Li W, Fay P, Ytterdal T, Seabaugh A (2018) Tunnel FET analog benchmarking and circuit design. IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 4(1):19–25. https://doi.org/10.1109/JXCDC.2018.2817541

    Article  Google Scholar 

  12. Trivedi, A.R., Amir, M.F. and Mukhopadhyay, S., 2014. Ultra-low power electronics with Si/Ge tunnel FET. In 2014 design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 1-6). IEEE. doi: https://doi.org/10.7873/DATE.2014.244

  13. Strangio S, Settino F, Palestri P, Lanuzza M, Crupi F, Esseni D, Selmi L (2018) Digital and analog TFET circuits: design and benchmark. Solid State Electron 146:50–65. https://doi.org/10.1016/j.sse.2018.05.003

    Article  CAS  Google Scholar 

  14. Guenifi N, Rahi SB, Larbi M (2020) Suppression of Ambipolar current and analysis of RF performance in double gate tunneling field effect transistors for low-power applications. Int J nanoparticles nanotech, 6, p.033. DOI. https://doi.org/10.35840/2631-5084/5533

  15. Guenifi N, Rahi SB, Ghodbane T (2018) Rigorous study of double gate tunneling field effect transistor structure based on silicon. Materials Focus 7(6):866–872. https://doi.org/10.1166/mat.2018.1600

    Article  CAS  Google Scholar 

  16. Datta S, Liu H, Narayanan V (2014) Tunnel FET technology: a reliability perspective. Microelectron Reliab 54(5):861–874. https://doi.org/10.1016/j.microrel.2014.02.002

    Article  Google Scholar 

  17. Lu H, Esseni D, Seabaugh A (2015) Universal analytic model for tunnel FET circuit simulation. Solid State Electron 108:110–117. https://doi.org/10.1016/j.sse.2014.12.002

    Article  CAS  Google Scholar 

  18. Sengupta D, Saleh R (2006) Generalized power-delay metrics in deep submicron CMOS designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26(1):183–189. https://doi.org/10.1109/TCAD.2006.883926

    Article  Google Scholar 

  19. Trivedi, A.R., Carlo, S. and Mukhopadhyay, S., 2013. Exploring tunnel-FET for ultra-low power analog applications: a case study on operational transconductance amplifier. In 2013 50th ACM/EDAC/IEEE design automation conference (DAC) (pp. 1-6). IEEE. doi: https://doi.org/10.1145/2463209.2488868

  20. Aparin V, Larson LE (2005) Modified derivative superposition method for linearizing FET low-noise amplifiers. IEEE Transactions on Microwave Theory and Techniques 53(2):571–581. https://doi.org/10.1109/TMTT.2004.840635

    Article  Google Scholar 

  21. Paras, N., Chauhan, S.S. Temperature sensitivity analysis of vertical tunneling based dual metal Gate TFET on analog/RF FOMs. Appl. Phys. A 125, 316 (2019) doi. .https://doi.org/10.1007/s00339-019-2621-x

  22. Singh, A. and Pandey, C.K. Improved DC Performances of Gate-all-around Si-Nanotube Tunnel FETs Using Gate-Source Overlap. Silicon, (2021).https://doi.org/10.1007/s12633-021-00957-0

  23. Pandey CK, Singh A, Chaudhury S (2020) Effect of asymmetric gate–drain overlap on ambipolar behavior of double-gate TFET and its impact on HF performances. Appl Phys A Mater Sci Process 126:225. https://doi.org/10.1007/s00339-020-3402-2

    Article  CAS  Google Scholar 

  24. Zhao Q et al (2015) Strained Si and SiGe nanowire tunnel FETs for logic and analog applications. IEEE Journal of the Electron Devices Society 3:103–114. https://doi.org/10.1109/JEDS.2015.2400371

    Article  Google Scholar 

  25. Wang, H., Chang, S., He, J., Huang, Q. and Liu, F., 2016. The dual effects of gate dielectric constant in tunnel FETs. IEEE journal of the Electron devices Society, 4(6), pp.445–450. (2016). doi: https://doi.org/10.1109/JEDS.2016.2610478

  26. Li D, Zhang B, Lou H, Zhang L, Lin X, Chan M (2015) Comparative Analysis of Carrier Statistics on MOSFET and Tunneling FET Characteristics. IEEE Journal of the Electron Devices Society. https://doi.org/10.1109/JEDS.2015.2475163

  27. Kumar D (2019) Performance evaluation of double gate tunnel FET based chain of inverters and 6-T SRAM cell. Engineering Research Express 1(2):025055. https://doi.org/10.1088/2631-8695/ab5f16

    Article  Google Scholar 

  28. Dash S, Mohanty SK, Mishra GP (2021) Segmented drain engineered tunnel field effect transistor for suppression of Ambipolarity. Silicon. https://doi.org/10.1007/s12633-021-00973-0

  29. Jung, Y.H., Kang, I.M. and Cho, S., 2019. Microwave analysis of SiGe heterojunction double-gate tunneling field-effect transistor through its small-signal equivalent circuit. International Journal of RF and Microwave Computer-Aided Engineering, 29(6), p.e21678

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Acknowledgments

Prof S.C. Misra (Indian Institute of Technology, Kanpur, India) for their useful suggestions.

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Authors and Affiliations

  1. LEA Electronics Department, University Mostefa Benboulaid of Batna 2, 05000, Batna, Algeria

    Guenifi Naima

  2. Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, 208016, India

    Shiromani Balmukund Rahi

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  1. Guenifi Naima
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Naima, G., Rahi, S.B. Low Power Circuit and System Design Hierarchy and Thermal Reliability of Tunnel Field Effect Transistor. Silicon 14, 3233–3243 (2022). https://doi.org/10.1007/s12633-021-01088-2

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