Skip to main content
Fachgebiete
Automobil + Motoren Bauwesen + Immobilien Business IT + Informatik Elektrotechnik + Elektronik Energie + Nachhaltigkeit Finance + Banking Management + Führung Marketing + Vertrieb Maschinenbau + Werkstoffe Versicherung + Risiko
DE
EN
Bücher
Zeitschriften
Themenseiten
Organisationspsychologie Projektmanagement Marketing Smart Manufacturing
Weitere Formate
Podcasts Webinare Technik Webinare Wirtschaft Kongresse Veranstaltungskalender Awards
Jetzt Einzelzugang starten
Zugang für Unternehmen
Referenzkunden
SLX-Digitalkonferenz: Zukunftswerkstatt 2024

Mehr Umsatz mit Top-Kontakten

Am 7. Mai erfahren Sie, wie Vertriebsteams Leadgenerierung, Leadnurturing und Leadstrategien effizient steuern können.
Erweiterte Suche
Anmelden
nach oben

2007 | Buch

ISPD 2005/2006 Placement Benchmarks Kapitel lesen Erstes Kapitel lesen

Modern Circuit Placement

Best Practices and Results

herausgegeben von: Gi-Joon Nam, Jason Cong

Verlag: Springer US

Buchreihe : Integrated Circuits and Systems

Enthalten in: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik"

Einloggen, um Zugang zu erhalten
insite
SUCHEN

Über dieses Buch

Modern Circuit Placement: Best Practices and Results describes advanced techniques in VLSI circuit placement which is one of the most important steps of the VLSI physical design flow. Physical design addresses the back-end layout stage of the chip design process. As technology scales down, the significance of interconnect optimization becomes much more important and physical design, particularly the placement process, is essential to interconnect optimization.

This book has four unique characteristics. First, it focuses on the most recent highly scalable placement techniques used for multi-million gate circuit designs, with consideration of many practical aspects of modern circuit placement, such as density and routability control, mixed-size placement support, and area I/O support. Second the book addresses dominant techniques being used in the field. This book includes all the academic placement tools that competed at the International Symposium on Physical Design (ISPD) placement contest in 2005 and 2006. Although these tools are developed by academia, many core techniques in these tools are being used extensively in industry and represent today’s advanced placement techniques. Third, the book provides quantitative comparison among the various techniques on common benchmark circuits derived from real-life industrial designs. The book includes significant amounts of analysis on each technique, such as trade-offs between quality-of-results (QoR) and runtime. Finally, analysis of the optimality of the placement techniques is included. This is done by utilizing placement benchmarks with known optimal solutions, yet with characteristics similar to real industrial designs.

Modern Circuit Placement: Best Practices and Results is a valuable tool and a must-read for graduate students, researchers and CAD tool developers in the VLSI physical synthesis and physical design fields.

Inhaltsverzeichnis

Frontmatter

Benchmarks

Frontmatter
1. ISPD 2005/2006 Placement Benchmarks
Benchmarks can contribute significantly to algorithm development of many fields by providing a common basis for quantitative measurement and comparison. The early MCNC benchmarks and ISPD98 benchmarks [1] helped the academic community significantly to measure the advances in physical design in 1990s. While still being used extensively in placement and floorplanning research, those benchmarks can no longer be considered representative of today’s physical design challenges. To further aid future advances in placement, new benchmark suites, dubbed as ISPD 2005/2006 Placement Benchmarks, have been released in conjunction with ISPD placement contests. There are total 16 benchmark circuits that are directly derived from modern industrial ASIC designs.
Gi-Joon Nam, Charles J. Alpert, Paul G. Villarrubia
2. Locality and Utilization in Placement Suboptimality
Placement is a critical step in VLSI design. Interconnect delay dominates system performance, and placement determines the interconnect more than any other step in physical design. The complexity of modern designs, however, makes estimation of suboptimality difficult [14, 16, 28]. Studies on simplified, synthetic benchmarks with known optimal-wire length placements (PEKO [7]) initially suggested that many leading tools may produce solutions with excess wire length from 60% up to 150% or more. These results have generated wide interest in both industry [13] and academia [19, 22, 28]. Recent progress in placement [1, 5, 6, 17] has reduced the wire length gap on PEKO to about 12–40%.
Jason Cong, Michalis Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie

Flat Placement Techniques

Frontmatter
3. DPlace: Anchor Cell-Based Quadratic Placement with Linear Objective
Although circuit placement has been studied for decades, it continuously attracts research attentions. The placement problems grow rapidly in both problem size and complexity. Some industry placement problems contain multimillion gates and excessive number of blockages [1,2]. In this chapter, we introduce DPlace, an anchor cell and diffusion spreading-based quadratic placement engine that can handle largescale placement problem.
Tao Luo, David Z. Pan
4. Kraftwerk: A Fast and Robust Quadratic Placer Using an Exact Linear Net Model
This chapter describes the quadratic placer called “Kraftwerk.” Kraftwerk is based on distributing the modules on the chip by using an additional force. The additional force is separated in this placer into two forces: hold force and move force. Both of these forces are determined without any heuristics. This novel systematic force modeling yields the robustness of our iterative placement algorithm by provably converging to an overlap-free placement.
Peter Spindler, Frank M. Johannes

Top-Down Partitioning-Based Techniques

Frontmatter
5. Capo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental Capability
In this chapter, we describe the robust and scalable academic placement tool Capo. Capo uses the min-cut placement paradigm and performs (a) scalable multiway partitioning, (b) routable standard-cell placement, (c) integrated mixed-size placement, (d) wire length-driven fixed-outline floorplanning as well as (e) incremental placement.
Jarrod A. Roy, David A. Papa, Igor L. Markov
6. Congestion Minimization in Modern Placement Circuits
In this chapter, we propose a placement tool called Dragon which deploys hierarchical techniques to place large-scale mixed size designs that may contain thousand of macro blocks and millions of standard cells [1–3]. Min-cut-based top-down approach is taken to handle the large complexity of designs and simulated annealing is used to minimize the total wire length. Min-cut partitioning should be aware of large macro cells and may result in bins with different sizes. During simulated annealing, different bin sizes have to be considered. The techniques discussed in this work can be easily incorporated into any hierarchical placement flow and effectively produce legal final layouts with a short runtime.
Taraneh Taghavi, Xiaojian Yang, Bo-Kyung Choi, Maogang Wang, Majid Sarrafzadeh

Multilevel Placement Techniques

Frontmatter
7. APlace: A High Quality, Large-Scale Analytical Placer
Modern design requirements have brought additional complexities to netlists and layouts. Millions of components, whitespace resources, and fixed/movable blocks are just a few to mention in the list of complexities.With these complexities in mind, placers are faced with the burden of finding an arrangement of placeable objects under strict wirelength, timing, and power constraints. In this chapter, we describe the architecture and novel details of our high quality, large-scale analytical placer APlace2 (and the subsequent APlace3) [26–28]. The performance of APlace2, has been recognized in the recent ISPD-2005 placement contest, and in this paper we disclose many of the technical details that we believe are key factors to its performance. We describe (1) a new clustering architecture, (2) a dynamically adaptive analytical solver, and (3) better legalization schemes and novel detailed placement methods. We also provide extensive experimental results on a number of benchmark sets, including the IBM ISPD’04, IBM-PLACE 2.0, ICCAD’04, ISPD’05, PEKO’05, ISPD’06, PEKO’06 as well as using the zero-change netlist transformation benchmarking framework.
Andrew B. Kahng, Sherief Reda, Qinke Wang
8. FastPlace: An Efficient Multilevel Force-Directed Placement Algorithm
Placement is a critical component in the physical synthesis design flow of large-scale integrated circuits and is a major contributor to timing closure results. It is often run multiple times during various stages of the physical synthesis flow. In addition, circuit sizes that need to be handled by placement algorithms are steadily increasing to over tens of millions of modules. Hence, it is necessary to have efficient and scalable placement algorithms that can produce high-quality solutions satisfying a variety of design objectives.
Natarajan Viswanathan, Min Pan, Chris Chu
9. mFAR: Multilevel Fixed-Points Addition-Based VLSI Placement
The rapid advance of VLSI technology has created an increasing demand for highquality placement tools. A placer has to deliver solutions that meet all the design requirements in a rapid fashion without wasting any computational resources. The nanometer technology makes it possible to integrate billions of transistors in a single chip. Such a design complexity, combined with the increasingly stringent market pressure, requires a very efficient implementation of the placement algorithms. A modern design scenario usually involves several iterations between the logic synthesis and physical design before timing closure can be achieved. From a design iteration point of view, an efficient placement algorithm is essential. Moreover, shrinking feature sizes introduce a full spectrum of deep submicron effects, such as interconnect dominance, crosstalk, IR drop, etc., which challenge the chip designers more than ever before. A placer needs to address explicitly timing, congestion, signal integrity, etc., so that the design can be signed off in a timely manner to meet the shrinking market window.
Bo Hu, Malgorzata Marek-Sadowska
10. mPL6: Enhanced Multilevel Mixed-Size Placement with Congestion Control
mPL6 consists of three basic ingredients: global placement by multilevel nonlinear programming [21], discrete graph-based macro legalization followed by linear-time scan-based standard-cell legalization [26], and detailed placement [26]. It is designed for speed and scalability, low wirelength results, adaptability to complex constraints, and robustness under low white space.
Tony F. Chan, Kenton Sze, Joseph R. Shinnerl, Min Xie
11. NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs
This chapter is focused on NTUplace3 [6], a large-scale mixed-size analytical placer that can handle modern placement considerations such as wirelength, preplaced blocks, and density. Like many modern placers, NTUplace3 consists of three major stages: global placement, legalization, and detailed placement. Global placement evenly distributes blocks and finds the best position for each block to minimize the target cost (e.g., wirelength). Then, legalization removes all overlaps among blocks and places standard cells row by row. Detailed placement further refines the solution.
Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang
12. Conclusion and Challenges
Placement is one of the most important steps in the RTL-to-GDSII synthesis process, as it directly optimize the interconnects, which have become the bottleneck in circuit and system performance in the nanometer process technologies.
Backmatter
Metadaten
Titel
Modern Circuit Placement
herausgegeben von
Gi-Joon Nam
Jason Cong
Copyright-Jahr
2007
Verlag
Springer US
Electronic ISBN
978-0-387-68739-1
Print ISBN
978-0-387-36837-5
DOI
https://doi.org/10.1007/978-0-387-68739-1

Neuer Inhalt

    Bildnachweise