FinFETs and Other Multi-Gate Transistors

General introduction of this Chapter shows the evolution of the SOI MOS transistor and retraces the history of the multigate concept. The advantages of multigate FETs in terms of electrostatic integrity and short-channel control are described, and the challenges posed by the appearance of novel effects, some of quantum-mechanical origin, are outlined.

Outlines the issues associated with multigate FET manufacturing. This chapter describes thin-fin formation techniques, advanced gate stack deposition and source/drain resistance reduction techniques. Issues related to fin crystal orientation and mobility enhancement via strain engineering are tackled as well.

This Chapter describes the physics behind the BSIM-CMG (Berkeley Short-channel IGFET Model – Common Multi-Gate) compact models for multigate MOSFETs. A compact model serves as a link between process technology and circuit design. It is a concise mathematical description of the device physics in the transistor. Some simplifications in the physics, however, can be made to enable fast computer analysis of device/circuit behavior.

The scaling of conventional planar CMOS is expected to become increasingly difficult due to increasing gate leakage and subthreshold leakage.[1-2] Multi-gate FETs such as FinFETs have emerged as the most promising candidates to extend the CMOS scaling into the sub-25nm regime.[3-4] The strong electrostatic control over the channel originating from the use of multiple gates reduces the coupling between source and drain in the subthreshold region and it enables the Multigate transistor to be scaled beyond bulk planar CMOS for a given dielectric thickness. Numerous efforts are underway to enable large scale manufacturing of multi-gate FETs. At the same time, circuit designers are beginning to design and evaluate multi-gate FET circuits.

A compact model serves as a link between process technology and circuit design. It is a concise mathematical description of the complex device physics in the transistor. A compact model maintains a fine balance between accuracy and simplicity. An accurate model stemming from physics basis allows the process engineer and circuit designer to make projections beyond the available silicon data (scalability) for scaled dimensions and also enables fast circuit/device co-optimization. The simplifications in the physics enable very fast analysis of device/circuit behavior when compared to the much slower numerical based TCAD simulations. It is thus necessary to develop a compact model of multi-gate FETs for technology/circuit development in the short term and for product design in the longer term.

This Chapter analyzes the electrostatics of the multigate MOS system. Using quantum-mechanical concepts, it describes electron energy quantization and the properties of a one-dimensional and two-dimensional electron gas. The effects of tunneling through thin gate dielectrics on the electron population of a device are studied as well.

This Chapter analyzes the behavior of electron mobility in different multigate structures comprising double-gate transistors, FinFETs, and silicon nanowires. Mobility in multiple gate devices is compared to that in single-gate devices and different approaches for improving the mobility in these devices, such as different crystallographic orientations and strained Si channels, are studied.

This Chapter describes the effects of ionizing radiations such as gamma rays and cosmic rays on SOI MOSFETs. These effects are extremely important in military, space and avionics applications. Multi-gate FETs show exceptional resistance to total-dose and single-event effects and could become the new standard in radiation-hardened electronics.

This Chapter describes the interrelationship between the multi-gate FET device properties and elementary digital and analog circuits, such as CMOS logic gates, SRAM cells, reference circuits, operational amplifiers, and mixedsignal building blocks. This approach is motivated by the observation that a cost-efficient, heterogeneous SoC integration is a key factor in modern IC design.

The basic idea behind this chapter is to describe the interrelationship between the MuGFET device properties and elementary digital and analog circuits, such as CMOS logic gates, SRAM cells, reference circuits, operational amplifiers, and mixed-signal building blocks. This approach is motivated by the observation that a cost-efficient, heterogeneous SoC integration is a key factor in modern IC design. Typical examples are GSM/EDGE baseband processors for cellular phones [1], low-power multimedia processors [2] and ultra-low-power IC’s for wireless sensor networks and ambient intelligent applications.[3] From a technical point of view, common feature of these SoC applications is that they are all operated in an active and leakage power-limited environment. The prospect that MuGFET devices offer reduced leakage currents and improved low-voltage performance compared to planar bulk devices on the one hand and the challenges caused when leaving the evolutionary scaling path of planar CMOS on the other hand motivates an early circuit investigation in close cooperation with technology development.