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2012 | Buch

Communication Centric Design Kapitel lesen Erstes Kapitel lesen

Reconfigurable Networks-on-Chip

verfasst von: Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu

Verlag: Springer New York

Enthalten in: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik"

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SUCHEN

Über dieses Buch

This book provides a comprehensive survey of recent progress in the design and implementation of Networks-on-Chip. It addresses a wide spectrum of on-chip communication problems, ranging from physical, network, to application layers. Specific topics that are explored in detail include packet routing, resource arbitration, error control/correction, application mapping, and communication scheduling. Additionally, a novel bi-directional communication channel NoC (BiNoC) architecture is described, with detailed explanation.

Written for practicing engineers in need of practical knowledge about the design and implementation of networks-on-chip; Includes tutorial-like details to introduce readers to a diverse range of NoC designs, as well as in-depth analysis for designers with NoC experience to explore advanced issues; Describes a variety of on-chip communication architectures, including a novel bi-directional communication channel NoC.

From the Foreword:

Overall this book shows important advances over the state of the art that will affect future system design as well as R&D in tools and methods for NoC design. It represents an important reference point for both designers and electronic design automation researchers and developers.

--Giovanni De Micheli

Inhaltsverzeichnis

Frontmatter

Introduction to Network-on-Chip

Frontmatter
Chapter 1. Communication Centric Design
Abstract
As the density of VLSI design increases, the complexity of each component in a system raises rapidly. To accommodate the increasing transistor density, higher operating frequencies, and shorter time-to-market pressure, multi-processor System-on-Chip (MP-SoC) architectures, which use bus structures for on-chip communication and integrate complex heterogeneous functional elements on a single die, are more and more required in today’s semiconductor industry. However, today’s SoC designers face a new challenge in the design of the on-chip interconnects beyond the evolution of an increasing number of processing elements. Traditional bus-based communication schemes, which lack of scalability and predictability, are not capable to keep up with the increasing requirements of future SoCs in terms of performance, power, timing closure, scalability, and so on. To meet the design productivity and signal integrity challenges of next-generation system designs, a structured and scalable interconnection architecture, Network-on-Chip (NoC), has been proposed recently to mitigate the complex on-chip communication problem.
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu
Chapter 2. Preliminaries
Abstract
Network-on-Chip is the term used to describe an architecture that has maintained readily designable solutions in face of communication-centric trends. In this chapter, we will briefly review some concepts on the design of an NoC router architecture. Various flow-control mechanisms with its corresponding router architecture and design considerations will be included in this chapter.
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu

Network-on-Chips Design Methodologies Exploration

Frontmatter
Chapter 3. Techniques for High Performance Noc Routing
Abstract
In an NoC, designing an efficient routing mechanism is critical to the performance. One crucial issue in the routing strategies is, under the premise of deadlock and livelock freedoms, how to enhance routing adaptivity in order to come up with a flexible and efficient use of the available routing resources. Key NoC performance metrics include low packet delivery latency and high throughput rate.
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu
Chapter 4. Performance-Energy Tradeoffs for Noc Reliability
Abstract
The NoC architecture promises reliable high performance low power on-chip communication. To realize such promises, performance-energy trade-off analysis is carried out in this chapter to compare two competing error control strategies: forward error correction (FEC) versus automatic re-transmission request (ARQ). Contrary to previously reported results, we show that the ARQ scheme would consume more power than the FEC scheme to offer the same level of reliability when the power consumption of the re-transmission buffers is factored into the equation. This new finding leads to the conclusion that FEC error control strategy is more suitable for NoC implementation compared to ARQ.
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu
Chapter 5. Energy-Aware Task Scheduling for Noc-Based DVS System
Abstract
For real time applications, time slacks of a preliminary task schedule may be exploited to conserve energy. This can be accomplished by leveraging the dynamic voltage scaling (DVS) technique to slow down clock frequency of certain cores as long as the deadline is met. In this chapter, the task of fine-tuning an existing task assignment and schedule and using DVS to lower the overall energy consumption is formulated as a graph-theoretic maximum weight clique (MWC) problem. An efficient heuristic algorithm is proposed to systematically solve this problem. A unique feature of our approach is concurrently applying DVS to slow down the execution of multiple tasks to achieve better energy savings. Extensive simulations are performed to compare this proposed algorithm against leading energy-aware task scheduling algorithm and DVS algorithm. Our algorithm exhibits 22% more energy savings than the Energy Aware Scheduling (EAS) algorithm. As for energy saving in DVS process, our MWC-based method provides a 97% saving improvement over the PV-DVS algorithm.
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu

Case Study: Bidirectional NoC (BiNoC) Architecture

Frontmatter
Chapter 6. Bidirectional Noc Architecture
Abstract
A Bidirectional channel Network-on-Chip (BiNoC) architecture is proposed in this chapter to enhance the performance of on-chip communication. In a BiNoC, each communication channel allows itself to be dynamically reconfigured to transmit flits in either direction.
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu
Chapter 7. Quality-of-Service in BiNoc
Abstract
A QoS-aware BiNoC architecture is proposed in this chapter to support guarantee-service (GS) traffic while reducing packet delivery latency. With the dynamically self-reconfigured bidirectional communication channels incorporated in BiNoC, as presented in Chap.​ 6, our proposed QoS-aware technique can promise more flexibility for various traffic flow patterns. Specifically, a novel inter-router communication protocol is proposed to prioritize bandwidth arbitration in favor of high-priority GS traffic flows. Multiple virtual-channels with prioritized routing policy are also implemented to facilitate data transmission with QoS considerations. Combining these architectural innovations, the QoS-aware BiNoC architecture can promise reduced latency of packet delivery and a more efficient channel resource utilization.
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu
Chapter 8. Fault Tolerance in BiNoC
Abstract
For fault-tolerant data-link connections, a novel Bi-directional Fault-Tolerant NoC (BFT-NoC) scheme that supports both static and dynamic channel failures is proposed in this chapter. Except for a little performance loss, BFT-NoC can keep the system in normal operation when multiple communication channels are either permanently broken or temporarily failed in an on-chip network. In contrast to the conventional fault-tolerant schemes based on detouring packets, the operation of BFT-NoC is transparent to the adopted routing algorithm. That is, BFT-NoC can be more seamless and efficient since changing routing rules between normal and fault-tolerant operation modes is needless. Accordingly, it is possible for BFT-NoC to perform better in both resource utilization and application feasibility compared with other detour-based schemes.
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu
Chapter 9. Energy-Aware Application Mapping for BiNoC
Abstract
Power-efficient scheduling is investigated for BiNoC architecture in this chapter. To minimize the power consumption of real time applications on BiNoC, time slacks in a preliminary schedule are exploited to conserve power. In addition to the processing units, wide variance in the link utilization of an NoC also leads to huge power saving if the link frequency can be tuned accurately to track the variations in bandwidth requirements. This can be accomplished by utilizing the DVS technique to scale the link voltage or frequency, as long as the deadline is met. An efficient power aware task and communication scheduling algorithm is proposed with a unique feature of utilizing the configurability of a bidirectional channel to trade the data transmission time for power expenditure. Extensive simulations are performed to compare the proposed algorithm against conventional Earliest-Deadline First (EDF) based algorithm on NoC.
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu
Chapter 10. Concluding Remarks
Abstract
In the first part of this book, we introduced a state-of-the-art on-chip interconnection network design and some of the important design problems of NoC. Then, in the second part of this book, many important design issues on NoC, including routing technique, reliability, and energy-aware application mapping, were described.
Sao-Jie Chen, Ying-Cherng Lan, Wen-Chung Tsai, Yu-Hen Hu
Backmatter
Metadaten
Titel
Reconfigurable Networks-on-Chip
verfasst von
Sao-Jie Chen
Ying-Cherng Lan
Wen-Chung Tsai
Yu-Hen Hu
Copyright-Jahr
2012
Verlag
Springer New York
Electronic ISBN
978-1-4419-9341-0
Print ISBN
978-1-4419-9340-3
DOI
https://doi.org/10.1007/978-1-4419-9341-0

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