High-/Mixed-Voltage Analog and RF Circuit Techniques for Nanoscale CMOS

The convergence of wireless and semiconductor industries will turn into reality the vision of fully autonomous and seamless wireless connectivity in the near future, via combining advanced nanoscale CMOS technologies with innovative hybrid-domain circuits and systems solutions [1, 2]. One aim inside this immense scope is to develop a smart-mobile-companion device with high performance, adaptive connectivity and high power efficiency. High performance is the essential ingredient to cope with the ever increasing add-on of functionalities in a small handheld device. Adaptive connectivity is to automatically select the best wireless link, maximizing the quality of service wherever and whenever possible. Power efficiency is to extend the active-use days without entailing a big battery, or worrying about the battery life after executing much of the device’s functionality. To reach these three goals the system chips consisting of many analog and radio frequency (RF) circuits play a key role. The aim of adaptive connectivity promotes a full integration of many different radio technologies such as WiFi, Global Positioning System (GPS), Bluetooth^TM, cellular and mmWave into one unit, calling for an unprecedented high level of complexity among system planning, architectures and circuits. The goal of maximizing hardware sharing without compromising the performances challenges the designers throughout the front-to-back-end development. Yet, advanced nanoscale CMOS technology constitutes, still today, the most promising platform of wireless products for its tremendous advance in speed, system-on-chip capability and maturity (to some extent).

Instead of just following the rapid downsizing of V _DD mixed-voltag/mixed-voltage RF and analog CMOS circuits and systems have emerged as a prospective alternative [1], to deal with the wireless technology trends such as software-defined radio and cognitive radio; both are hungry for bandwidth and dynamic range. An elevated V _DD, or a hybrid use of I/O and core V _DD’s, in conjunction with optimum selection of thin- and thick-oxide MOSFETS open up much new design possibilities in re-defining circuit topologies, while maintaining most speed and area benefits of advanced fine linewidth processes [2]. Voltage-conscious bias techniques and overdrive protection circuits are simple and low overhead techniques to ensure the reliability of all devices. This chapter studies the basic design concept, system design considerations and some state-of-the-art circuit examples. A wide variety of analog and RF CMOS circuits featuring high-/mixed-V _DD is discussed. Those circuits comprise power amplifier, low-noise amplifier, mixer, operational-amplifier-based analog circuits, sample-and-hold amplifier and line driver. Reliability metrics such as oxide breakdown voltage, hot carrier injection (HCI), time dependent dielectric breakdown (TDDB), and bias temperature instability (BTI) will be briefly addressed. The involved concepts and techniques are generally extendable to different wireless and non-wireless applications.

This chapter presents a number of circuit techniques enforced in the design of an electrostatic discharge (ESD)-protected ultra-wideband (UWB) low-noise amplifier (LNA) for mobile-TV applications. Unlike the design of narrowband LNAs, concurrent reception over a wide range of spectrum necessitates the LNA to feature high linearity, preventing desensitization by the high-power blockers. This requirement, in conjunction with the obvious design goals of ESD protected input, low noise figure (NF), low power, impedance match and high gain, constitute hard tradeoffs to obtain a sensible balance and good compromise among all. The proposed LNA is to cover the full band of mobile-TV services from 170 to 1,700 MHz such that only one LNA is necessary to support multiple standards. It features a PMOS-based open-source input structure to optimize the I/O swings under a mixed-voltage ESD protection while offering an inductorless broadband input impedance match. The amplification core exploiting double current reuse and single-stage thermal-noise cancellation enhances the gain and noise performances with high power efficiency. Optimized in a 90-nm 1.2/2.5-V CMOS process with practical issues taken into account, the LNA using a constant-g _m bias circuit achieves competitive and robust performances over process, voltage and temperature (PVT) variation. The simulated voltage gain is 20.6 dB, noise figure is 2.4–2.7 dB and IIP3 is +10.8 dBm. The power consumption is 9.6 mW at 1.2 V. |S₁₁| < –10 dB is achieved up to 1.9 GHz without needing any external resonant network. Human Body Model ESD zapping tests of ±4 kV at the input pins cause no failure of any device.

High-voltage (HV)-enabled circuits offer a feasible alternative to cope with the sub-1 V technologies at low cost. This chapter describes the first 2 × V _DD-enabled mobile-TV RF front-end with TV-GSM interoperability. It is an on/off-chip co-design employing externally three customized UHF/VHF preselect filters, a RF switch and a balun. The integrated part includes: (1) a cascode-cascade inverter-based low-noise amplifier that features a high gain-to-power efficiency; (2) a linearized C-2C attenuator using reliable-overdriven MOS switches; (3) an inductive-peaking feedforward path that evens out the passband variation; and (4) two cascode I/Q mixer drivers capable to drive passive mixers with small gain and bandwidth reduction. Gate-drain-source engineering and self-biased structures are the keys enabling performance optimization with low power and no reliability risk. Fabricated in a 90-nm CMOS process with 1-V thin-oxide devices, the RF front-end measures 68-dB rejection at GSM-900 uplink, 0.7-dB passband roll-off, 3.9-dB noise figure and −5.5-dBm IIP3 at a maximum voltage gain of 26.2 dB. The core occupies 0.28 mm² and draws 15 mW. The achieved power-performance metrics is favorably comparable with the prior arts.

With improved device parasitics in nm-length CMOS processes, wideband RF circuits offer the desired compactness and power efficiency for realizing multi-band multi-standard radios. This chapter describes a receiver front-end (RFE) targeting the mobile-TV applications using mixed-voltage techniques. It covers the VHF-III (174–248 MHz), UHF (470–862 MHz) and L (1.4–1.7 GHz) bands, where standards like T-DMB, ISDB-T, DVB-H and DMB-T are resided. In order to meet the noise and linearity specifications [1], while avoiding external baluns or repeated RFEs that were still common in existing solutions [1, 2], a number of circuit techniques are proposed to enhance the performance, power and area efficiencies [3]. Together they lead to state-of-the-art performance, while saving 58% area compared to the 1.1 mm² reported in [2]. The key design considerations are outlined as follows.

Technology downscaling has stressed the use of sub-1V V _DD to maintain device reliability. In this book, high-/mixed-voltage RF and analog CMOS circuits have been presented as the technology comes of age, being apposite for realizing high-performance wireless systems in ultra-scaled CMOS technologies. Dual voltage supplies have become very common since the deployment of nm-length CMOS processes such as the 90-nm node. We also believe that multiple supplies offering a V_DD-on-demand approach will be more efficient in overall system power savings. This book explored a number of analog and RF circuit techniques. From block level to sub-system level, the techniques led to enhanced performances, lower power and cost. When design-for-reliability (i.e., prevent overstress on any device) is included in the design flow, an elevated V _DD outpacing the technology roadmap directly opens up more flexibility in defining circuit topologies while preserving sufficient voltage headroom for signal swing. Table 6.1 summarizes the design considerations of analog and RF circuits with different degrees of freedom, namely area, current and the topic of this research, supply.