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Erschienen in:
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2013 | OriginalPaper | Buchkapitel

High-Performance Computing Based on High-Speed Dynamic Reconfiguration

verfasst von : Minoru Watanabe

Erschienen in: High-Performance Computing Using FPGAs

Verlag: Springer New York

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Abstract

Currently, demand for implementing all systems including a processor, a peripheral circuit, and a dedicated circuit onto a field programmable gate array (FPGA) is gaining. However, related to the demand, an important issue is that soft-core processors implemented on FPGAs have lower performance than custom processors or FPGA’s hard-core processors. Such low performance of soft-core processors on FPGAs is attributable to their look-up table (LUT) and Switching Matrix (SM) architectures. Therefore, under current implementation, such a soft-core processor cannot be used to produce a high-performance system. Instead, a custom processor or an FPGA’s hard-core processor must be implemented onto the system along with an FPGA. However, if the FPGA’s programmability can be exploited fully, then the performance of soft-core processors and circuits on its programmable gate array can be increased. The key technology is a high-speed dynamic reconfiguration. Therefore, this chapter introduces a new soft-core processor architecture called Mono-Instruction Set Computer (MISC) architecture as high-performance computing based on high-speed dynamic reconfiguration.

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Vorheriges Kapitel MEMSCALE: Re-architecting Memory Resources for Clusters
Nächstes Kapitel Reconfigurable Arithmetic for High-Performance Computing
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Metadaten
Titel
High-Performance Computing Based on High-Speed Dynamic Reconfiguration
verfasst von
Minoru Watanabe
Copyright-Jahr
2013
Verlag
Springer New York
Buch
High-Performance Computing Using FPGAs

Print ISBN: 978-1-4614-1790-3

Electronic ISBN: 978-1-4614-1791-0

Copyright-Jahr: 2013

DOI
https://doi.org/10.1007/978-1-4614-1791-0_20

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