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2001 | Buch

Introduction Kapitel lesen Erstes Kapitel lesen

Principles of Asynchronous Circuit Design

A Systems Perspective

herausgegeben von: Jens Sparsø, Steve Furber

Verlag: Springer US

Enthalten in: Professional Book Archive

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Über dieses Buch

Principles of Asynchronous Circuit Design - A Systems Perspective addresses the need for an introductory text on asynchronous circuit design. Part I is an 8-chapter tutorial which addresses the most important issues for the beginner, including how to think about asynchronous systems. Part II is a 4-chapter introduction to Balsa, a freely-available synthesis system for asynchronous circuits which will enable the reader to get hands-on experience of designing high-level asynchronous systems. Part III offers a number of examples of state-of-the-art asynchronous systems to illustrate what can be built using asynchronous techniques. The examples range from a complete commercial smart card chip to complex microprocessors.
The objective in writing this book has been to enable industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task.

Inhaltsverzeichnis

Frontmatter

Asynchronous Circuit Design — A Tutorial

Frontmatter
Chapter 1. Introduction
Abstract
Most digital circuits designed and fabricated today are “synchronous”. In essence, they are based on two fundamental assumptions that greatly simplify their design: (1) all signals are binary, and (2) all components share a common and discrete notion of time, as defined by a clock signal distributed throughout the circuit.
Jens Sparsø, Steve Furber
Chapter 2. Fundamentals
Abstract
This chapter provides explanations of a number of topics and concepts that are of fundamental importance for understanding the following chapters and for appreciating the similarities between the different asynchronous design styles. The presentation style will be somewhat informal and the aim is to provide the reader with intuition and insight.
Jens Sparsø, Steve Furber
Chapter 3. Static Data-Flow Structures
Abstract
In this chapter we will develop a high-level view of asynchronous design that is equivalent to RTL (register transfer level) in synchronous design. At this level the circuits may be viewed as static data-flow structures. The aim is to focus on the behaviour of the circuits, and to abstract away the details of the handshake signaling which can be considered an orthogonal implementation issue.
Jens Sparsø, Steve Furber
Chapter 4. Performance
Abstract
In this chapter we will address the performance analysis and optimization of asynchronous circuits. The material extends and builds upon the “static data-flow structures view” introduced in the previous chapter.
Jens Sparsø, Steve Furber
Chapter 5. Handshake Circuit Implementations
Abstract
In this chapter we will address the implementation of handshake components. First, we will consider the basic set of components introduced in section 3.3 on page 32: (1) the latch, (2) the unconditional data-flow control elements join, fork and merge, (3) function blocks, and (4) the conditional flow control elements MUX and DEMUX. In addition to these basic components we will also consider the implementation of mutual exclusion elements and arbiters and touch upon the (unavoidable) problem of metastability. The major part of the chapter (sections 5.3–5.6) is devoted to the implementation of function blocks and the material includes a number of fundamental concepts and circuit implementation styles.
Jens Sparsø, Steve Furber
Chapter 6. Speed-Independent Control Circuits
Abstract
This chapter provides an introduction to the design of asynchronous sequential circuits and explains in detail one well-developed specification and synthesis method: the synthesis of speed-independent control circuits from signal transition graph specifications.
Jens Sparsø, Steve Furber
Chapter 7. Advanced 4-Phase Bundled-Data Protocols and Circuits
Abstract
The previous chapters have explained the basics of asynchronous circuit design. In this chapter we will address 4-phase bundled-data protocols and circuits in more detail. This will include: (1) a variety of channel types, (2) protocols with different data-validity schemes, and (3) a number of more sophisticated latch control circuits. These latch controllers are interesting for two reasons: they are very useful in optimizing the circuits for area, power and speed, and they are nice examples of the types of control circuits that can be specified and synthesized using the STG-based techniques from the previous chapter.
Jens Sparsø, Steve Furber
Chapter 8. High-Level Languages and Tools
Abstract
This chapter addresses languages and CAD tools for the high-level modeling and synthesis of asynchronous circuits. The aim is briefly to introduce some basic concepts and a few representative and influential design methods. The interested reader will find more details elsewhere in this book (in Part II and chapter 13) as well as in the original papers that are cited in the text. In the last section we address the use of VHDL for the design of asynchronous circuits.
Jens Sparsø, Steve Furber

Balsa — An Asynchronous Hardware Synthesis System

Frontmatter
Chapter 9. An Introduction to Balsa
Abstract
Balsa is both a framework for synthesising asynchronous hardware systems and a language for describing such systems. The approach adopted is that of syntax-directed compilation into communicating handshaking components and closely follows the Tangram system ([141, 135] and Chapter 13 on page 221) of Philips. The advantage of this approach is that the compilation is transparent: there is a one-to-one mapping between the language constructs in the specification and the intermediate handshake circuits that are produced. It is relatively easy for an experienced user to envisage the micro-architecture of the circuit that results from the original description. Incremental changes made at the language level result in predictable changes at the circuit implementation level. This is important if optimisations and design trade-offs are to be made easily and contrasts with synchronous VHDL synthesis in which small changes in the specification may make radical alterations to the resulting circuit.
Jens Sparsø, Steve Furber
Chapter 10. The Balsa Language
Abstract
In this chapter, a tutorial overview of the language is given together with several small designs which illustrate various aspects of the language.
Jens Sparsø, Steve Furber
Chapter 11. Building Library Components
Abstract
Parameterised procedures allow designers to develop a library of commonly used components and then to instantiate those structures later with varying parameters. A simple example is the specification of a buffer as a library part without knowing the width of the buffer. Similarly, a pipeline of buffers can be defined in the library without requiring any knowledge of the depth chosen for the pipeline when it is instantiated.
Jens Sparsø, Steve Furber
Chapter 12. A Simple DMA Controller
Abstract
A simple 4 channel DMA controller is presented as a practical description of a reasonably large-scale Balsa design written entirely in Balsa and so can be compiled for any of the technologies which the Balsa back-end supports. Readers should note that this controller is not the same as the Amulet3i DMA controller referred to in chapter 15. A more detailed description of this controller and the motivation for its design can be found in [8]. A complete listing of the code for the controller can be downloaded from [7].
Jens Sparsø, Steve Furber

Large-Scale Asynchronous Designs

Frontmatter
Chapter 13. Descale
a Design Experiment for a Smart Card Application consuming Low Energy
Abstract
We have designed an asynchronous chip for contactless smart cards. Asynchronous circuits have two power properties that make them very suitable for contactless devices: low average power and small current peaks. The fact that asynchronous circuits operate over a wide range of the supply voltage, while automatically adapting their speed, has been used to obtain a circuit that is very resilient to voltage drops while giving maximum performance for the power being received. The asynchronous circuit has been built, tested and evaluated.
Joep Kessels, Ad Peeters, Torsten Kramer, Volker Timm
Chapter 14. An Asynchronous Viterbi Decoder
Abstract
Viterbi decoders are used for decoding data encoded using convolutional forward error correcting codes. Such codes are used in a large proportion of digital transmission and digital recording systems because, even when the transmitted signal is subjected to significant noise, the decoder is still able efficiently to determine the most likely transmitted data.
This chapter descibes a novel Viterbi decoder aimed at being power efficient through adopting an asynchronous approach. The new design is based upon serial unary arithmetic for the computation and storage of the metrics required; this arithmetic replaces the add-compare-select parallel arithmetic performed by conventional synchronous systems. Like all Viterbi decoders, a history of computational results is built up over many data bits to determine the data most likely to have been transmitted at an earlier time. The identification of a starting point to this tracing operation allows the storage requirement to be greatly reduced compared with that in conventional decoders where the starting point is random. Furthermore, asynchronous operation in the system described enables multiple, independent, concurrent tracing operations to be performed which are decoupled from the placing of new data in the history memory.
Linda E. M. Brackenbury
Chapter 15. Processors
Abstract
Computer design becomes ever more complex Small asynchronous systems may be intriguing and even elegant but unless asynchronous logic can not only be competitive with ‘conventional’ logic but can show some significant advantages it cannot be taken seriously in the commercial world.
There can be no better way to demonstrate the feasibility of something than by doing it. To this end several research groups around have the world have been putting together real, large, asynchronous systems. These have taken several forms, but many groups have chosen to start with microprocessors; a processor is a good demonstrator because it is well defined, self-contained and forces a designer to solve problems which are already well understood. If an asynchronous implementation of a microprocessor can compare favourably with a synchronous device performing an identical function then the case is proven.
This chapter describes a number of processors that have been fabricated and discusses in some detail some of the solutions employed. The primary source of the material is the Amulet series of ARM implementations — because these are the most familiar to the author — but other devices are included as appropriate. The later parts of the chapter widen the descriptions to include memory systems, cacheing and on-chip interconnect, illustrating how a complete asynchronous System on Chip (SoC) can be produced.
Jim D. Garside

Epilogue

Epilogue
Abstract
Asynchronous technology has existed since the first days of digital electronics — many of the earliest computers did not employ a central clock signal. However, with the development of integrated circuits the need for a straightforward design discipline that could scale up rapidly with the available transistor resource was pressing, and clocked design became the dominant approach. Today, most practising digital designers know very little about asynchronous techniques, and what they do know tends to discourage them from venturing into the territory. But clocked design is beginning to show signs of stress — its ability to scale is waning, and it brings with it growing problems of excessive power dissipation and electromagnetic interference.
Jens Sparsø, Steve Furber
Backmatter
Metadaten
Titel
Principles of Asynchronous Circuit Design
herausgegeben von
Jens Sparsø
Steve Furber
Copyright-Jahr
2001
Verlag
Springer US
Electronic ISBN
978-1-4757-3385-3
Print ISBN
978-1-4419-4936-3
DOI
https://doi.org/10.1007/978-1-4757-3385-3