Skip to main content

Quantum Mechanical Potential Modeling of FinFET

  • Chapter
  • First Online:
Toward Quantum FinFET

Part of the book series: Lecture Notes in Nanoscale Science and Technology ((LNNST,volume 17))

Abstract

This chapter focus on a full Two-Dimensional (2D) Quantum Mechanical (QM) analytical modeling in order to evaluate the 2D potential profile within the active area of FinFET structure. Various potential profiles such as surface, back to front gate, and source to drain potential have been presented in order to appreciate the usefulness of the device for circuit simulation purposes. As we move from source end of the gate to the drain end of the gate, there is substantial increase in the potential at any point in the channel. This is attributed to the increased value of longitudinal electric field at the drain end on application of a drain to source voltage. Further, in this chapter, the detailed study of threshold voltage and its variation with the process parameters is presented. A threshold voltage roll-off with fin thickness is observed for both theoretical and experimental results. The fin thickness is varied from 10 to 60 nm. From the analysis of S/D resistance, it is observed that for a fixed fin width, as the channel length increases, there is an enhancement in the parasitic S/D resistance. This can be inferred from the fact as the channel length decreases, quantum confinement along the S/D direction becomes more extensive. For our proposed devices a close match is obtained with the results through analytical model and reported experimental results, thereby validating our proposed QM analytical model for DG FinFET device.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. International Technology Roadmap for Semiconductors (ITRS), Semiconductor Industry Association, San Jose, CA (2007)

    Google Scholar 

  2. Chaudhry, A., Kumar, M.J.: Controlling short-channel effect in deep-submicron SOI MOSFETs for improved reliability: a review. IEEE Trans. Dev. Mater. Reliab. 4(3), 99–109 (2004)

    Article  Google Scholar 

  3. Ortiz-Conde, A., García-Sánchez, F.J., Malobabic, S.: Analytical solution of the channel potential in undoped symmetric dual-gate MOSFETs. IEEE Trans. Electron Dev. 52(7), 1669–1672 (2005)

    Article  ADS  Google Scholar 

  4. Frank, D.J.: Power-constrained CMOS scaling limits. IBM J. Res. Dev. 46, 235–244 (2002)

    Article  Google Scholar 

  5. Havaldar, D.S., Katti, G., DasGupta, N., DasGupta, A.: Subthreshold current model of FinFETs based on analytical solution of 3-D Poisson’s equation. IEEE Trans. Electron Dev. 53(4), 737–742 (2006)

    Article  ADS  Google Scholar 

  6. Chen, Q., Harrell, E.M., Meindl, J.D.: A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs. IEEE Trans. Electron Dev. 50(7), 1631–2581 (2003)

    Article  ADS  Google Scholar 

  7. Pei, G., Kedzierski, J., Oldiges, P., Ieong, M., Kan, E.C.-C.: FinFET design considerations based on 3-D simulation and analytical modeling. IEEE Trans. Electron Dev. 49(8), 1411–1419 (2002)

    Article  ADS  Google Scholar 

  8. Dixit, A., Kottantharayil, A., Collaert, N., Goodwin, M., Jurczak, M., De Meyer, K.: Analysis of the parasitic S/D resistance in multiple-gate FET. IEEE Trans. Electron Dev. 52(6), 1132–1139 (2005)

    Article  ADS  Google Scholar 

  9. Hisamoto, D., Lee, W.C., Kedzierski, J., Takeuchi, H., Asano, K., Kuo, C., Anderson, E., King, T.J., Bokor, J., Hu, C.: FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans. Electron Dev. 47, 2320–2325 (2000)

    Article  ADS  Google Scholar 

  10. Colinge, J.P.: Multiple-gate SOI MOSFET. Solid State Electron. 48, 897–905 (2004)

    Article  ADS  Google Scholar 

  11. Colinge, J.P.: Silicon-on-insulator technology: materials to VLSI. Kluwer Academic, Dordrecht (1991)

    Book  Google Scholar 

  12. Tang, S.H., Chang, L., Lindert, N., Choi, Y.K., Lee, W.C., Huang, X., Subramanian, V., King, T.J., Bokor, J., Hu, C.: FinFET – a quasiplanar double gate MOSFET. In: Proceedings of international solid-state circuits conference (ISSCC), pp. 118–119 (2001)

    Google Scholar 

  13. Hodges, D.A.: Analysis and design of digital integrated circuits, 3rd edn. Tata McGraw-Hill, New Delhi (2003)

    Google Scholar 

  14. Moore, G.E.: Cramming more components onto integrated circuits. Electronics 38(8), 114–117 (1965)

    Google Scholar 

  15. Chang, L.: Nanoscale thin-body CMOS devices. Ph.D. dissertation, University of California, Berkeley, Department of Electrical Engineering and Computer Sciences (2003)

    Google Scholar 

  16. Yeap, G.: Practical low power digital VLSI design. Kluwer Academic, Boston (1998)

    Book  Google Scholar 

  17. Kang, S.M., Leblebici, Y.: CMOS digital integrated circuits, 3rd edn. Tata McGraw-Hill, New Delhi (2003)

    Google Scholar 

  18. Lázaro, A., Nae, B., Moldovan, O., Iñiguez, B.: A compact quantum model of nanoscale metal-oxide semiconductor field effect transistor for high frequency and noise simulations. J. Appl. Phys. 100(8), 4320–4332 (2006)

    Article  Google Scholar 

  19. Ortiz Conde, A., Sánchez, F.J.G., Schmidt, P.E., Sa Neto, A.: The non-equilibrium inversion layer charge of the thin-film SOI MOSFET. IEEE Trans. Electron Dev. 36(9), 1651–1656 (1989)

    Article  ADS  Google Scholar 

  20. Suzuki, K., Tanaka, T., Tosaka, Y., Horie, H., Arimoto, Y.: Scaling theory for double-gate SOI MOSFET’s. IEEE Trans. Electron Dev. 40, 2326–2329 (1993)

    Article  ADS  Google Scholar 

  21. Oh, S.H., Monroe, D., Hergenrother, J.M.: Analytic description of short channel effects in fully-depleted Double-Gate and cylindrical, surrounding gate MOSFET. IEEE Electron Device Lett. 21(9), 445–447 (2000)

    Article  ADS  Google Scholar 

  22. Arora, N.: MOSFET models for VLSI circuits simulations theory and practice, 1st edn. Springer, New York (1993)

    Book  Google Scholar 

  23. Katti, G., DasGupta, N., DasGupta, A.: Threshold voltage model for mesa-isolated small geometry fully depleted SOI MOSFETs based on analytical solution of 3-D Poisson’s equation. IEEE Trans. Electron Dev. 51(7), 1169–1177 (2004)

    Article  ADS  Google Scholar 

  24. Kedzierski, J., Ieong, M., Nowak, E., Kanarsky, T.S., Zhang, Y., Roy, R., Boyd, D., Fried, D., Wong, H.S.P.: Extension and source/drain design for high-performance FinFET devices. IEEE Trans. Electron Dev. 50(4), 952–958 (2003)

    Article  ADS  Google Scholar 

  25. Tsui, B.Y., Lin, C.P.: Process and characteristics of modified Schottky barrier (MSB) p-channel FinFET. IEEE Trans. Electron Dev. 52(11), 2455–2462 (2005)

    Article  ADS  Google Scholar 

  26. Hu, W., Chen, X., Zhou, X., Quan, Z., Lu, W.: Quantum-mechanical effects and gate leakage current of nanoscale n-type FinFETs: a 2D simulation study. Microelectron. J. 37, 613–619 (2006)

    Article  Google Scholar 

  27. Rabaey, J.M., Chandrakasan, A., Nikolic, B.: Digital integrated circuits, 2nd edn. Prentice Hall, Upper Saddle River (2002)

    Google Scholar 

  28. Uyemura, J.P.: Introduction to VLSI circuit and systems. Wiley, New York (2002)

    Google Scholar 

  29. Roy, K., Prasad, S.: Low power CMOS VLSI circuit design. Wiley Interscience, New York (2000)

    Google Scholar 

  30. Itoh, K.: Review and future prospects of low-voltage memory circuits. IBM J. Res. Dev. 525–552 (2003)

    Google Scholar 

  31. Yan, R.H., Ourmazd, A., Lee, K.F.: Scaling the Si MOSFET: from bulk to SOI to bulk. IEEE Trans. Electron Dev. 39, 1704–1710 (1992)

    Article  ADS  Google Scholar 

  32. Verheyen, P., Collaert, N., Rooyackers, R., Loo, R., Shamiryan, D., De Keersgieter, A., Eneman, G., Leys, F., Dixit, A., Goodwin, M., Yim, Y.S., Caymax, M., De Meyer, K., Absil, P., Jurczak, M., Biesemans, S.: 25% Drive current improvement for P-type multiple gate FET (MuGFET) devices by introduction of recessed Si0.8Ge0.2 in the source and drain regions. In: Symposium on VLSI technology, pp. 194–195 (2005)

    Google Scholar 

  33. Granzner, R., Schwierz, F., Polyakov, V.M.: An analytical model for the threshold voltage shift caused by 2D quantum confinement in undoped multiple-gate MOSFETs. IEEE Trans. Electron Dev. 54, 2562–2565 (2007)

    Article  ADS  Google Scholar 

  34. Kolberg, S., Fjeldly, T.A.: 2D modeling of DG SOI MOSFETs and near the subthreshold regime. J. Comput. Electron. 52(2), 217–222 (2006)

    Article  Google Scholar 

  35. Taur, Y.: Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFET. IEEE Trans. Electron Dev. 48(12), 2861–2869 (2001)

    Article  ADS  Google Scholar 

  36. Monfray, S., Skotnicki, T., Morand, Y., Descombes, S., Coronel, P., Mazoyer, P., Harrison, S., Ribot, P., Talbot, A., Dutartre, D., Haond, M., Palla, R., Le Friec, Y., Leverd, F., Nier, M.E., Vizioz, C., Louis, D.: 50 nm-gate all around (GAA)-silicon on nothing (SON) devices: a simple way to Co-integration of GAA transistors within bulk MOSFET process. In: Symposium on VLSI technology. Digest of technical papers, pp. 108–109 (2002)

    Google Scholar 

  37. Munteanu, D., Autran, J.L., Loussier, X., Harrison, S., Cerutti, R., Skotnicki, T.: Quantum short-channel compact modeling of drain-current in double-gate MOSFET. Elsevier Solid State Electron. 50, 680–686 (2006)

    Article  ADS  Google Scholar 

  38. Harrison, S., Munteanu, D., Autran, J.L., Cros, A., Cerutti, R., Skotnicki, T.: Electrical characterization and modeling of high-performance SON DG MOSFETs. In: Proceedings of European solid-state device research conference (ESSDERC), pp. 373–376 (2004)

    Google Scholar 

  39. Chiang, M.H., Lin, C.N., Lin, G.S.: Threshold voltage sensitivity to doping density in extremely scaled MOSFETs. Semicond. Sci. Technol. 21, 190–193 (2006)

    Article  ADS  Google Scholar 

  40. Trivedi, V.P., Fossum, J.G., Vandooren, A.: Non-classical CMOS device design. In: Proceedings of IEEE international SOI conference, pp. 155–157 (2003)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Balwinder Raj .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2013 Springer International Publishing Switzerland

About this chapter

Cite this chapter

Raj, B. (2013). Quantum Mechanical Potential Modeling of FinFET. In: Han, W., Wang, Z. (eds) Toward Quantum FinFET. Lecture Notes in Nanoscale Science and Technology, vol 17. Springer, Cham. https://doi.org/10.1007/978-3-319-02021-1_4

Download citation

Publish with us

Policies and ethics