5. Multi-Standard Digital Front-End Processing

To demonstrate flexibility and performance of the reconfigurable cell array architecture introduced in Chap. 4, this chapter presents a case study of the platform configured for concurrent processing of multiple radio standards. Flexibility of the architecture is demonstrated by performing time synchronization and Carrier frequency offset (CFO) estimation for multiple Orthogonal frequency division multiplexing (OFDM)-based standards. As a proof-of-concept, this study focuses on three contemporarily widely used radio standards, 3GPP Long term evolution (LTE), IEEE 802.11n, and Digital video broadcasting for handheld (DVB-H). The employed reconfigurable cell array, containing 2 × 2 resource cells, supports all three standards and is capable of processing two concurrent data streams. The cell array is implemented in a 65 nm CMOS technology, resulting in an area of 0.48 mm² and a maximum clock frequency of 534 MHz. Dynamic configuration of the cell array enables run-time switching between different standards and allows adoption of different algorithms on the same platform. Taking advantage of the in-cell configuration scheme (described in Chap. 4), context switching between different operation scenarios requires at most 11 clock cycles. The implemented 2 × 2 cell array is fabricated as a part of a Digital front-end (DFE) Receiver and is measured as a standalone module via an on-chip serial debugging interface. Running at 10 MHz clock frequency and at 1.2 V supply voltage, the array reports a maximum power consumption of 2.19 mW during the processing of IEEE 802.11n data receptions and 2 mW during hardware configurations.