Silicon Nanowire Transistors

In the past, there were several attempts to develop alternative technologies, including molecular technologies that were aimed to replace the current VLSI technology. However, conventional silicon-based technologies prevailed as solid choices over the newcomers for fabricating low power nano devices and circuits without sacrificing high performance. As today’s chips require larger die areas to accommodate complex System-On-Chip (SOC) designs, reducing overall power dissipation has been accepted as the major design objective, replacing the need for faster circuit performance. Recent modeling studies in undoped, double-gated SOI MOS transistors revealed that these transistors could produce an order of magnitude less leakage current compared to conventional bulk silicon MOS transistors for achieving ultra-low power consumption. However, fabricating ultra-thin transistors sandwiched between two gates with adjustable work function is highly questionable in a production environment since both gates have to be made out of metal in order to produce proper threshold voltage and therefore to maintain a healthy circuit operation. Another good candidate is a nano-scale, triple-gated SOI transistors or FINFETs. Recent studies on these devices showed close-to-ideal subthreshold slope and Drain-Induced-Barrier-Lowering (DIBL), both of which are important factors to reduce OFF current and power consumption. Besides these promising technologies, Silicon Nanowire MOS Transistors (SNT) also offer significant reduction in static and dynamic power consumption and compact layout area without sacrificing circuit performance.

This chapter first examines the device design process of dual work function SNTs to achieve minimum power dissipation. It then studies the circuit performance, static and dynamic power figures of basic CMOS logic gates and mega cells built with SNTs.

In the first chapter of this book, SNTs with dual work function gates were designed and their device characteristics were examined. Later in the same chapter, basic digital CMOS gates were built; their circuit performance, power dissipation, and layout characteristics were analyzed; basic SNT processing steps were shown. A dual work function CMOS technology requires the use of different metals in NMOS and PMOS transistor gates. Finding the appropriate metals that match exactly to the work function values found in this study may often be a difficult enterprise as it may require alloys for gate material or incompatible metals with the SNT processing. One way to reduce the set of problems associated with dual metals is to use a single metal gate. Therefore, this chapter is dedicated to design NMOS and PMOS transistors with a single work function metal gate, and furthermore use these transistors in designing CMOS circuits.

In Chapters 1 and 2, we studied the device and digital circuit aspects of dual and single work function SNTs with the intention to minimize power dissipation. Both of these studies have determined that silicon nanowire technology is better suited for the future of VLSI in terms of circuit speed and power dissipation compared to dual-gated SOI or FiNFET technologies. These studies also included the weaknesses of SNTs such as increased layout area due to surrounding gate metal thickness, large source resistance caused by source contact extension, and limited ON current caused by fixed transistor geometry. In Chapters 1 and 2, SPICE level 6 models were used in circuit simulations. While these models had acceptable accuracy in producing speed and power dissipation figures for basic CMOS logic gates, more accurate intrinsic device modeling and parasitic RC extraction were required for simulating larger scale digital circuits, analog circuits, and Radio Frequency (RF) circuits. This need prompted us to explore more accurate SPICE models such as BSIMSOI for fully depleted Silicon-On-Insulator (SOI) devices to use in the circuit simulations. This chapter examines how the intrinsic and extrinsic BSIMSOI models were created for NMOS and PMOS SNTs.

In Chapter 3, we obtained accurate BSIMSOI SPICE models for NMOS and PMOS silicon nanowire transistors to replicate the simulated device I–V characteristics. We also calculated voltage-dependent intrinsic gate oxide capacitance, parasitic device resistors and capacitors, including the high frequency effective gate resistance in order to generate accurate extrinsic circuit models for SNTs. This chapter presents the first application of silicon nanowire technology on analog circuits. Various small and large-signal analog circuits such as a single-stage CMOS amplifier, a differential pair amplifier, and a two-stage operational amplifier were designed and simulated using the BSIMSOI SPICE models of SNTs.

This chapter presents the application of silicon nanowire technology on another analog domain: RF receivers. RF receivers contain two important functional blocks. The first block is the down-converter unit. This block consists of a low noise amplifier, a mixer, and an oscillator. It is mainly used to translate a high frequency signal to a lower frequency signal for baseband processing. The second block is the Variable Gain Amplifier (VGA). Because the signal strength largely depends on the distance between the receiver and transmitter, the VGA regulates the signal strength before the re-conditioned signal arrives at the input of the baseband processor. The design approach and the circuits incorporating SNTs are fully examined in this chapter to design and analyze both of these units. The layout of each SNT includes a re-engineered source structure as well as extra gate and source contacts to minimize high terminal resistances as they deteriorate the overall noise factor of the RF receiver and make the input impedance matching difficult.

The primary objective of this chapter is to present the application of silicon nanowire technology on a first large-scale digital mega cell design: an SRAM. The detailed steps of generating accurate BSIMSOI SPICE models from vertically-grown SNTs with undoped bodies and dual work function metal gates were already discussed in Chapter 3. This chapter uses the SNT device models in the design and analysis of a 16 × 16 SRAM block and reports the circuit simulation results and electrical data.

To be able to implement large-scale SOC designs, minimizing overall power dissipation is a critical. The primary objective of this chapter is to present the results of silicon nanowire technology in a widely utilized prototyping platform called Field-Programmable Gate Array (FPGA). The proposed FPGA architecture in this chapter uses cluster blocks, each of which includes several Look-Up-Tables (LUT) to configure any logic functionality. Each LUT can be configured as a combinatorial logic block or part of a state machine. This flexible configuration is achieved by scan chains implemented inside the cluster block to define the interconnectivity between LUTs and to determine the logic functionality for each LUT. After describing the architectural aspects of the LUT and the cluster, circuit simulations were performed using BSIMSOI SNT models. The chapter reports the results of worst-case propagation delays and power dissipation figures of various FPGA circuits and shows typical LUT and the cluster layouts.

This chapter applies the benefits of silicon nanowire technology yet to another interesting digital design area: designing a digital neuron. A neuron is an essential element to mimic brain-like processing functions such as recognition, perception, and it is composed of three parts: dendrites, soma, and axon. Electric impulses are transmitted to dendrites via a few thousand synapses, a postsynaptic potential is generated at soma, and an impulse is generated and distributed among neighboring neurons via synapses attached to the axon. To associate this behavior in VLSI, a realistic implementation of this device is necessary. This chapter uses extrinsic BSMSOI SNT models generated in Chapter 3 to perform circuit design and simulations of a digital neuron. It reports electrical data including performance and power consumption figures of a single neuron cell and its layout.

As today’s mixed signal chips often require both digital and analog system components on the same substrate, an interesting area of application for silicon nanowire technology is to build a Direct Sequence Spread Spectrum (DSSS) baseband transmitter. A basic baseband transmitter contains an 8-Phase Shift Keying (8-PSK) modulator, a fourth order PN generator, a binary bit mapper, and two bit multipliers. This chapter uses the BSIMSOI models of NMOS and PMOS SNTs developed in Chapter 3 to simulate all transmitter circuits and shows the design and analysis of a typical DSSS baseband transmitter. All electrical data and the transmitter layout are included in this chapter.