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2018 | OriginalPaper | Buchkapitel

5. Comparator

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Abstract

In different architectures introduced throughout the years, the comparator is a necessary circuit block. It plays an important role not only in the accuracy, but also in the speed of the data conversion. In this chapter, we discuss how to provide a comparator for a power-efficient and high-performance ADC. First, the circuit techniques that help to relax the requirements of the comparator are presented. Both the redundancy technique and the reference voltage stabilization technique are described. Second, we make a step to the design considerations of the dynamic comparator, including the speed and power dissipation, the noise, the offset, and the kickback noise. At the end of the chapter, we sum up the comparator design for the power-efficient and high-performance ADC.

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Literatur
1.
Zurück zum Zitat B. Razavi, Principles of Data Conversion Systems (IEEE Press, New York, 1995) B. Razavi, Principles of Data Conversion Systems (IEEE Press, New York, 1995)
2.
Zurück zum Zitat P.E. Allen, D.R. Holberg, Cmos Analog Circuit Design, 2nd edn (Oxford University Press, New York, 2002), pp. 483–484 P.E. Allen, D.R. Holberg, Cmos Analog Circuit Design, 2nd edn (Oxford University Press, New York, 2002), pp. 483–484
3.
Zurück zum Zitat D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl, B. Nauta, A double-tail latch-type voltage sense amplifier with 18ps setup+hold time, in 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, Feb 2007, pp. 314–605 D. Schinkel, E. Mensink, E. Klumperink, E. van Tuijl, B. Nauta, A double-tail latch-type voltage sense amplifier with 18ps setup+hold time, in 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, Feb 2007, pp. 314–605
4.
Zurück zum Zitat M. Miyahara, Y. Asada, D. Paik, A. Matsuzawa, A low-noise self-calibrating dynamic comparator for high-speed adcs, in 2008 IEEE Asian Solid-State Circuits Conference, Nov 2008, pp. 269–272 M. Miyahara, Y. Asada, D. Paik, A. Matsuzawa, A low-noise self-calibrating dynamic comparator for high-speed adcs, in 2008 IEEE Asian Solid-State Circuits Conference, Nov 2008, pp. 269–272
5.
Zurück zum Zitat K. Uyttenhove, M.S.J. Steyaert, A 1.8-v 6-bit 1.3-ghz flash adc in 0.25-\(\mu \)m cmos. IEEE J. Solid-State Circuits 38, 1115–1122 (2003)CrossRef K. Uyttenhove, M.S.J. Steyaert, A 1.8-v 6-bit 1.3-ghz flash adc in 0.25-\(\mu \)m cmos. IEEE J. Solid-State Circuits 38, 1115–1122 (2003)CrossRef
6.
Zurück zum Zitat P.M. Figueiredo, J.C. Vital, Kickback noise reduction techniques for cmos latched comparators. IEEE Trans. Circuits Syst. II: Express Briefs 53, 541–545 (2006)CrossRef P.M. Figueiredo, J.C. Vital, Kickback noise reduction techniques for cmos latched comparators. IEEE Trans. Circuits Syst. II: Express Briefs 53, 541–545 (2006)CrossRef
7.
Zurück zum Zitat P. Amaral, J. Goes, N. Paulino, A. Steiger-Garcao, An improved low-voltage low-power cmos comparator to be used in high-speed pipeline adcs, in 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), vol. 5, pp. V–141–V–144, 2002 P. Amaral, J. Goes, N. Paulino, A. Steiger-Garcao, An improved low-voltage low-power cmos comparator to be used in high-speed pipeline adcs, in 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), vol. 5, pp. V–141–V–144, 2002
Metadaten
Titel
Comparator
verfasst von
Weitao Li
Fule Li
Zhihua Wang
Copyright-Jahr
2018
DOI
https://doi.org/10.1007/978-3-319-62012-1_5

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