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2017 | OriginalPaper | Buchkapitel

Your Rails Cannot Hide from Localized EM: How Dual-Rail Logic Fails on FPGAs

verfasst von : Vincent Immler, Robert Specht, Florian Unterstein

Erschienen in: Cryptographic Hardware and Embedded Systems – CHES 2017

Verlag: Springer International Publishing

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Abstract

Protecting cryptographic implementations against side-channel attacks is a must to prevent leakage of processed secrets. As a cell-level countermeasure, so called DPA-resistant logic styles have been proposed to prevent a data-dependent power consumption.

As most of the DPA-resistant logic is based on dual-rails, properly implementing them is a challenging task on FPGAs which is due to their fixed architecture and missing freedom in the design tools.

While previous works show a significant security gain when using such logic on FPGAs, we demonstrate this only holds for power-analysis. In contrast, our attack using high-resolution electromagnetic analysis is able to exploit local characteristics of the placement and routing such that only a marginal security gain remains, therefore creating a severe threat.

To further analyze the properties of both attack and implementation, we develop a custom placer to improve the default placement of the analyzed AES S-box. Different cost functions for the placement are tested and evaluated w.r.t. the resulting side-channel resistance on a Spartan-6 FPGA. As a result, we are able to more than double the resistance of the design compared to cases not benefiting from the custom placement.

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Vorheriges Kapitel Fast Leakage Assessment

Nächstes Kapitel How to Break Secure Boot on FPGA SoCs Through Malicious Hardware

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We omitted results from probes with 100 \(\upmu \)m and 250 \(\upmu \)m due to similarity reasons. In contrast, a probe with 3 mm was almost equivalent to a power-based measurement.

\(\mathrm {d} = \mathrm {abs}(x_s - x_m) + \mathrm {abs}(y_s - y_m)\), i.e., the rectangular distance over the grid.

Our results can also be mapped onto BCDL [28] since it is similar to DPLnoEE.

At a later point in time, \(en_o\) becomes active in order to check the correct functionality of the circuit. This is not covered by the recorded power and EM traces.

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Titel: Your Rails Cannot Hide from Localized EM: How Dual-Rail Logic Fails on FPGAs
verfasst von: Vincent Immler
Robert Specht
Florian Unterstein
Verlag: Springer International Publishing
Buch: Cryptographic Hardware and Embedded Systems – CHES 2017
Print ISBN: 978-3-319-66786-7

Electronic ISBN: 978-3-319-66787-4

Copyright-Jahr: 2017
DOI: https://doi.org/10.1007/978-3-319-66787-4_20

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