2010 | OriginalPaper | Buchkapitel
ABC: An Academic Industrial-Strength Verification Tool
verfasst von : Robert Brayton, Alan Mishchenko
Erschienen in: Computer Aided Verification
Verlag: Springer Berlin Heidelberg
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ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transformations based on And-Inverter Graphs (AIGs), with a variety of innovative algorithms. A focus on the synergy of sequential synthesis and sequential verification leads to improvements in both domains. This paper introduces ABC, motivates its development, and illustrates its use in formal verification.