Compact Modeling

We review surface-potential-based approach to compact modeling of bulk MOS transistors and provide introduction to the widely used PSP model jointly developed by the Arizona State University and NXP Semiconductors. The emphasis is on the interplay between the mathematical structure of the compact model and its capabilities for the circuit design applications.

Surface-potential-based models, which represent the mainstream approach to compact modeling of bulk MOSFETs, are now in the process of being applied to SOI devices. In this chapter we discuss two advanced SOI models—PSP-SOI-PD for partially depleted devices and PSP-SOI-DD including the dynamic depletion effects. Both models are based on the popular PSP model of bulk MOSFETs. The theoretical foundation of all PSP-family models is the symmetric linearization method that allows one to raise the physical contents of the compact model without prohibitive increase in its computational complexity. In addition to the physics-based structure of the new models inherited from bulk PSP, they account for phenomena specific to SOI devices (e.g. floating body, and valence band tunneling current) and include a detailed description of parasitic effects. We discuss both the theoretical developments and verification of the model against test data and TCAD simulations with particular emphasis on the interplay between the model structure and its simulation capabilities.

It has long been recognized that, apart from computational efficiency and accuracy of fitting experimental data, compact MOS transistor models should exhibit qualitatively correct physical behavior for drain current, terminal charges, noise, and all derivatives. Physics-based models may automatically embody the correct physical behavior for long-channel devices, but compact models of scaled transistors inevitably involve approximations that can introduce unphysical qualitative characteristics. Over time, several “benchmark tests” were developed to ensure that transistor characteristics predicted by a compact model satisfy the needs of the circuit designers, especially for analog and mixed-signal design. As the importance of RF CMOS circuits increases, the requirements for qualitatively correct physical behavior of compact MOSFET models are becoming more stringent (for example, it is now common to require the existence of fifth order derivatives) and several new benchmark tests, targeted for RF design needs, were developed. This chapter describes both traditional and newly developed MOSFET model benchmark tests and applies them to the PSP model.

In many new applications like communication and automotive electronics the usage of integrated high voltage MOS transistors (LDMOS and DMOS) requires highly accurate compact models. In this chapter we present a deep look into special LDMOS transistor behavior and discuss state of the art sub-circuit modeling with BSIM/EKV core and JFET/Resistor approach. Parasitic diode and bipolar effects are discussed and modeling suggestions are presented. The EKV high voltage model developed by Swiss Federal Institute of Technology (EPFL) and the MM20 high voltage model introduced by NXP Research (formerly Philips Research) Laboratories is demonstrated in detail. The first CMC (Compact Modeling Council) standard high voltage MOSFET model HiSIM_HV developed by Hiroshima University is explained as well. Finally, characterization and measurement strategies for LDMOS modeling are described.

This chapter reviews the operation and modeling of bipolar junction transistors (BJTs) and heterojunction bipolar transistors (HBTs). The emphasis is on fundamental device physics and modeling; subsequent chapters give specific details of two advanced models, Mextram and HiCuM. We first give a synopsis of basic BJT device behavior and modeling, and then introduce the Gummel integral charge control relationship, which elegantly and physically encapsulates the core description of BJT operation. The development of approximations to this key relationship, which leads to the widely known and used SGP (SPICE Gummel-Poon) model, are detailed, as are modifications necessary for modeling III-V HBT devices.

We present the Mextram model, an industrial world standard compact model for bipolar transistors, showing the identity, philosophy and capabilities of the model. Mextram has been developed to capture all terminal characteristics of bipolar transistors that are relevant to industrial electronic circuit design of any Si or SiGe bipolar transistor, under all relevant practical circumstances. History, basic structure and features of the model are discussed, including simulation of heating effects, noise, geometrical scaling and statistical analysis. The relevance of the refined topology of its equivalent circuit, to simulation of advanced ac-characteristics of modern high-speed Si and SiGe transistors is extensively demonstrated.

This chapter provides an overview on the advanced compact bipolar transistor model HiCuM in terms of the modelling approach with respect to circuit design. The relevant physical effects occurring in modern heterojunction bipolar transistors (HBTs) are briefly described with the main focus on SiGe HBTs. Geometry scaling, a statistical design methodology, and parameter extraction methods in an industrial environment are discussed. These methods are applied step by step to a selected advanced SiGe HBT process technology with a transit frequency beyond 200 GHz. The corresponding results for a consistent set of important device characteristics exhibit excellent agreement over bias, temperature and geometry, and demonstrate the suitability of the model for such high-frequency bipolar process technologies.

This chapter details models for resistors. Although resistors may seem to be simple devices, in practice the effects of velocity saturation, depletion pinching, and self-heating cause the dc I(V) characteristics to be nonlinear, and for this nonlinearity to vary with geometry and temperature. Even slight nonlinearities in resistors can contribute significantly to distortion and harmonics in highly linear analog and RF circuits, so accurate modeling of the nonlinearities is needed. Parasitics and self-heating also cause the ac behavior of resistors to vary with frequency. Basics of resistor modeling are reviewed, and a physically based 3-terminal resistor model is derived, and shown to be applicable to both poly resistors and diffused resistors (which are really JFETs). The model includes geometry and temperature dependence, and also has statistical variability, including mismatch, built in. Details of some useful parameter extraction procedures are provided.

The physics-based junction model for CMOS, called JUNCAP2, is described. It contains single-piece formulations for the Shockley-Read-Hall generation/recombination current and the trap-assisted tunneling current which are valid both in forward and reverse mode of operation. Moreover, the trap-assisted tunneling model extends the previous model (Hurkx et al. in IEEE Trans. Electron Devices 39(9), 2090–2098, 1992) to the high electric fields encountered in today’s CMOS technologies. Furthermore, the model contains expressions for junction capacitance, ideal current, band-to-band tunneling current, avalanche breakdown, and junction shot noise. The parameter extraction, experimental verification and a calculationally efficient evaluation procedure (JUNCAP2 Express) are also discussed in this chapter. The JUNCAP2 model is incorporated in the PSP model for bulk MOSFET’s (see Chap. 1 of this book) and in the PSP-SOI model for SOI MOSFET’s (see Chap. 2 of this book).

A surface-potential-based scalable model for MOS varactors was developed jointly by Arizona State University, Sentinel IC Technologies, Jazz Semiconductor, and Freescale Semiconductor to facilitate RF CMOS design. We give details of the model, which is based on PSP, and show how it fits key device characteristics, including capacitance, gate current, and quality factor as functions of voltage, frequency, and geometry, for several technologies. Recent advances in the parameter extraction procedure are also reviewed. The model is implemented in Verilog-A and provides a robust and accurate description of MOS varactors, including their RF performance. A VCO design application is presented to illustrate the capabilities of the new model.

The challenge for accurate modeling of on-chip RF passive components, L/C/R, lies on the proper consideration of undesired parasitics and capturing of distributed nature of the structure at high frequency. This is especially true for inductive components, namely inductors and transformers including baluns, because of the open capacitive and (long-range) magnetic couplings between the top widing metal layers and the lossy silicon substrate.

This chapter is mostly focused on the equivalent circuit modeling (i.e., compact modeling) of spiral inductors and transformers, while the modeling of on-chip resistors and capacitors are briefly mentioned. Among the modeling of spirals inductive components, the emphasis is on the calculation and extraction of three key parameters: inductance L (and for transformers also the magnetic coupling coefficient k between the primary and secondary windings), quality factor Q, and self-resonant frequency SRF (due to inevitable parasitic capacitance across the port of the inductor). Both one-π and two-π circuit topologies for inductor modeling are reviewed with tilt toward the former because of its renaissance recently. The discussion on transformer modeling is largely based on the seminal work by Long (IEEE J. Solid-State Circuits 35(9):1368, 2000). Up-to-date circuit applications of spiral transformers are provided as a motivation of studying this important subject.

As the scaling of conventional planar CMOS is reaching its limits, multiple-gate CMOS structures will likely take up the baton. To facilitate circuit simulation in such advanced technologies, we have developed BSIM-MG: a versatile compact model for multi-gate MOSFETs. In this chapter separate formulations for common multi-gate and independent multi-gate MOSFETs are presented. The core I-V and C-V models are derived and agree well with TCAD simulations without using fitting parameters, reflecting the predictivity and scalability of the model. Physical effects such as volume inversion, short channel effects and quantum mechanical effects are included in the model. We verify BSIM-MG against triple-gate SOI FinFET experimental data. The model fits data very well across a wide range of biases, gate lengths and temperatures. It is also computationally efficient and suitable for simulating large circuits. Finally, several multi-gate circuit simulation examples are presented to demonstrate the use of the model.

This chapter reviews recent developments on compact modeling of double-gate and nanowire MOSFETs. It starts with the core, long-channel drain current models of double-gate and nanowire MOSFETs, derived from the analytic solutions of 1-D Poisson and current continuity equations in Cartesian and cylindrical coordinates, respectively. Explicit and continuous solutions to the implicit parameters in both models have been developed. The short-channel models based on the scale length approach to the boundary value problems of 2-D Poisson’s equation in subthreshold are then described, followed by charge and capacitance models for both double-gate and nanowire MOSFETs. A popular, surface-potential based current expression in the literature is examined before concluding the chapter.

Circuit operation greatly depends on the ability to control and reproduce transistor and process parameters, such as oxide thickness, dielectric constants, doping levels, width and length. Variation in processing was in the past countered by defining process corners: boundaries in parameter variation that accounted for remaining process tolerances. With the improved control over processing, this batch-to-batch variation is largely under control.

However now a new class of phenomena has appeared: statistical variations. In conventional ICs, analog circuits with a differential operation (e.g. analog-to-digital converters) were already affected by this random parameter spread. The remaining variation between otherwise identical components is generally described by “mismatch” parameters. Next to these random phenomena also systematic errors called “offsets” play an increasingly important role Understanding and mitigating these effects requires statistical means and models.

The chapter will focus on the modeling of systematic and random effects that originate from physical, electrical, thermal and lithographical effects in devices causing intra-die variations.

This chapter reviews statistical modeling for circuit simulation, with an emphasis on the backward propagation of variance (BPV) technique. Sources of variability are reviewed, and a formulation based on uncorrelated process parameters is presented. A general procedure for modeling variances of electrical performances is detailed, including handling of nonlinearities and correlations, and numerical properties of the procedure are discussed. Approaches to generating corner models are reviewed, and the importance of properly modeling correlations is demonstrated.